[SI-LIST] Re: clock divider

Sort of sounds like a flip-flop with Q and _Q outputs

Tom Dagostino
Teraspeed Consulting Group LLC     Teraspeed Consulting Group LLC
2926 SE Yamhill St.                Device Modeling Division
Portland, OR 97214                 13610 SW Harness Lane
                                   Beaverton, OR 97008
http://www.teraspeed.com           503-430-1065 
tom@xxxxxxxxxxxxx 


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ahmet Tokuz
Sent: Wednesday, November 26, 2003 3:03 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] clock divider


Hello,

I was wondering whether there's a way of dividing
clock by 2 deterministicly. I mean there may be two
outputs.  However I am interested in the one with
where phase is synched. I mean both rising and falling
edges are aligned. Are there any way to ensure that?

thanks



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