[SI-LIST] Re: bypass-caps: trade-off between capacitance and inductance

Sarah,

You seem to be in the fortunate situation of knowing the
board your package will go onto.  Since you say via in pad
is not allowed, it would be a good idea to check with the
board designers and/or assembly people to see if they
have any feedback for you on the two planned pinouts.
It looks to me that even if you stagger the vias in the
via field to make more room for the capacitors, fitting
in all the pads you need (via pads and capacitor pads)
may violate some people's manufacturing rules.

Regarding the choice between the two outlined options,
you will need to take a step back and look at the
interfacing impedances: the total capacitance of these
0402 caps interfaces with the inductance of the
board with all of the optional other capacitors
placed further away from the package.  The total
inductance of these caps will interface with the
package: optional package capacitors and die capacitance.
This is where a specific final answer cannot be given
without knowing at least roughly the assumed PCB stackup
(you may or may not know this) and the total number of
pins in this particular via array (you know this for sure).
For instance, if you have hundreds of power/ground vias
in this array, the vertical via indiuctance from all of
these vias will be much less than the inductance of the
horizontal plane path.  In this case, the coupling of
the adjacent vias in the via field may matter much
less (because you will get a low number anyway),
but the placement of capacitors does matter.   So in
this case you may be better off going with your option 1.
If you have a small number of power/ground vias,
their cumulative inductance will not be negligible to the
horizontal plane inductance.  In this case the capacitor
placement matters less, and you may want to minimize
the vertical via inductance by selecting optimum via
pattern that minimizes via inductance through coupling
(this was your option 2), and you even could move some
or all of the capacitors outside of the package footprint.

Best regards,

Istvan Novak
SUN Microsystems

Sarah Bates wrote:

>Si-folk,
>I am pinning-out a chip that will be used on a board that
>does not use via-in-pad technology.  In order to place
>bypass caps in the 1mm ball field, I'll need to place 2 power
>balls in a row and two ground balls adjacent to the power balls,
>and drop an 0402 cap in between them.  In order to maximize the number
>of caps, I could then keep adding a pair of power and gnd balls,
>and a cap.  However, this will place all powers in one row and
>all grounds in aonther row and so the mutual inductance of the
>caps/vias in the power-delivery path will be increased.  If I
>try to alternate power and ground, I will not be able to place
>as many caps, so how do I go about quantifying the trade-off between
>the two scenarios.  (Scenario 1 is having more caps, but a topology
>in-which the mutual-inductance works against me.  Scenario 2 is
>having fewer caps, but alternating occasionally so that the mutual-
>inductance works for me.)
>For this analysis, I'm estimating a 10 layer board and via inductance
>on the order of 0.9nH.  I think this is reasonable.  I would use 0.1uF
>0402 caps.
>
>Here are pictures to clarify the question:
>P represents a power ball
>G represents a ground ball
>|| represents an 0402 capacitor
>
>Scenario 1:
>P  P  P  P  P  P  P  P  P  P  P  P
> || || || || || || || || || || ||
>G  G  G  G  G  G  G  G  G  G  G  G
>
>
>Scenario 2:
>P  P  P  G  G  G  P  P  P  G  G  G
> || ||    || ||    || ||    || ||
>G  G  G  P  P  P  G  G  G  P  P  P
>
>Please point me to any relevant books/papers if you know of any.
>
>Thanks,
>Sarah
>
>
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