[SI-LIST] bypass-caps: trade-off between capacitance and inductance

Si-folk,
I am pinning-out a chip that will be used on a board that
does not use via-in-pad technology.  In order to place
bypass caps in the 1mm ball field, I'll need to place 2 power
balls in a row and two ground balls adjacent to the power balls,
and drop an 0402 cap in between them.  In order to maximize the number
of caps, I could then keep adding a pair of power and gnd balls,
and a cap.  However, this will place all powers in one row and
all grounds in aonther row and so the mutual inductance of the
caps/vias in the power-delivery path will be increased.  If I
try to alternate power and ground, I will not be able to place
as many caps, so how do I go about quantifying the trade-off between
the two scenarios.  (Scenario 1 is having more caps, but a topology
in-which the mutual-inductance works against me.  Scenario 2 is
having fewer caps, but alternating occasionally so that the mutual-
inductance works for me.)
For this analysis, I'm estimating a 10 layer board and via inductance
on the order of 0.9nH.  I think this is reasonable.  I would use 0.1uF
0402 caps.

Here are pictures to clarify the question:
P represents a power ball
G represents a ground ball
|| represents an 0402 capacitor

Scenario 1:
P  P  P  P  P  P  P  P  P  P  P  P
 || || || || || || || || || || ||
G  G  G  G  G  G  G  G  G  G  G  G


Scenario 2:
P  P  P  G  G  G  P  P  P  G  G  G
 || ||    || ||    || ||    || ||
G  G  G  P  P  P  G  G  G  P  P  P

Please point me to any relevant books/papers if you know of any.

Thanks,
Sarah


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