[SI-LIST] Re: bypass caps on unused pcb area
- From: Duane Mattheisen <duane.mattheisen@xxxxxxx>
- To: istvan Novak <Istvan.Novak@xxxxxxx>, "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
- Date: Tue, 30 Sep 2008 01:47:51 +0200
Loyer and Jeff,
I once had a circuit with ~100 dB of gain and the current from the output
would flow through the ground plane and out the ground connection near the
input of the amplifiers. This ground current flowing near the input amplifier
would cause oscillations. We fixed this problem by moving the ground
connection to the middle of the four stage amplifier and we cut some of the
ground plane so the output currents going into the ground would leave through
the ground connection before having a chance to get back to the input of the
amplifier.
Regards,
Duane Mattheisen
NXP
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of istvan Novak
Sent: 2008 Sep 24 3:56 PM
To: Loyer, Jeff
Cc: steve weir; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: bypass caps on unused pcb area
Joel, Jeff,
As always, it depends. As it was pointed out, left-alone power-ground
cavities will have a series of modal resonances, the lowest being
inversely proportional to the largest linear dimension of the cavity.
If nothing excites the cavity, or nothing gets bothered by the
resonance, it is perfectly fine to leave it open.
The cavity resonances will get excited by vertical currents going
through the cavities: noisy power or ground vias for chip power
connections and signal vias. Having the vertical loop smaller will
reduce the effect, so tightly coupled differential signals will excite
these cavities the least, and power-ground pins of large ASIC
core footprints tend to excite the most.
What may get bothered by the resonance: signals (single ended and
differential alike) referencing the bouncy plane, even if the other
reference plane in the stripline is ground. This is an SI issue,
and boards can fail because of this. The other risk is potential EMC
radiation from chips, whose power is riding on the noisy plane.
This might be a smaller issue in practice, plus in this case
tightening the enclosure is a way out. These resonances usually create
the least problem for power deliver, as the power distribution interface
between the board and chip (going through the package) tends to
be a low-pass filter, attenuating the board noise enough that it wont
upset the chip. Exception is sensitive analog power pins (like PLL
supply pins), but for those we dont have the luxury to attach large
unused plane areas.
In terms of solutions, in case you need to eliminate these resonances,
you can use area capacitors or dissipative components to reduce
the problem (no solution will cure it 100%). With area
capacitors, we just break up the large cavity into many smaller
cavities, so the lowest resonance frequency is pushed out to
higher values. In practice in todays medium or large-size PCBs,
a spacing around an inch (or couple of centimeters) prove to be enough
for most cases. Another possibility is to dampen the resonances with
RCs or with high-ESR capacitors. This second solution always
require fewer components (and less board area for the parts) because
we have to place these parts around the periphery as opposed to
the area, and with the same spacing between parts, filling the
perimeter takes fewer parts than filling the area.
This problem is not theoretical-only, it happens in real life. I
witnessed weeks of debugging of intermittent differential links
just to find out that the unstable link picked up burst noise from
a reference plane, which was left without bypass capacitors
over some length along the diff-pair route. The noise on the
plane originated from a chip in one area of the plane. The chip
was well bypassed, noise at the chip was very small. At the
quarter-wave resonances the noise current dumped into the
well-bypassed plane was turned into large bursts further away,
where no component was connected to the plane.
Regards,
Istvan Novak
Sun Microsystems
Loyer, Jeff wrote:
> Another (theoretical) reason occurs to me. I haven't experienced this
> particular problem, and am not sure it can happen in real life (I'm sure it's
> possible in theory), but would appreciate others' thoughts.
>
> Is it reasonable to envisage a resonance that is set up so that there is
> significant noise on power planes in the middle of an area that has no
> components, but has acceptable noise at the agents? Perhaps you might see
> acceptable noise at the agents on the periphery of this area, but the noise
> from several agents adds up in the middle to an unacceptable level. Common
> practice would be to only add caps at the agents. If there is routing
> adjacent to the noisy power plane, that noise would be induced on that
> routing.
>
> But, there are 2 (at least) possible problems:
> 1) no way to monitor the noise in the "bare" area between agents (at least
> easily)
> 2) no way to address the noise in the "bare" area between agents
>
> These have led me to think that putting some empty cap sites in "bare" areas
> might be a good idea. I haven't seen this particular problem, but
> investigating other noise issues led me to wonder...
>
> Your thoughts?
>
> Jeff Loyer
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of steve weir
> Sent: Tuesday, September 23, 2008 2:12 PM
> To: Joel Brown
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: bypass caps on unused pcb area
>
> Joel, yes but not quite for the reason you state. As long as the
> capacitor distribution is not egregiously non uniform, AND ignoring
> capacitance of attached ICs, then the bypass to plane cross-over
> frequency depends on:
>
> 1. The mounted inductance of each capacitor
> 2. The capacitance per square inch of plane cavity, which is to say
> 225pF*eR/H ( H in mils )
> 3. The capacitor density per square inch
>
> The two effects of leaving large unbypassed plane areas are:
>
> 1. The cross-over frequency comes down.
> 2. If the area has a long extent in one direction or another then modal
> resonance can be worse which is unpleasant if it aligns to something
> coherent like a clock or clock / 2. The ways that cavities get excited:
> a. An IC draws current through the cavity.
> b. Signals inject into the cavity such as when a signal references the
> top plane goes through a via and then references the bottom plane, or
> signals cross moats.
>
> Steve.
> Joel Brown wrote:
>
>> Is it a good idea to sprinkle bypass on areas of a pcb that are otherwised
>> not used except for power / ground planes?
>> The idea being to keep the power / ground planes from creating a resonance
>> and radiating.
>> Could such a resonace be exicted if there are no traces or components
>> nearby?
>> If so, how do we determine the interval of placement. We have no simulation
>> tools to help us.
>>
>>
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