[SI-LIST] Re: bypass caps on unused pcb area

Another (theoretical) reason occurs to me.  I haven't experienced this 
particular problem, and am not sure it can happen in real life (I'm sure it's 
possible in theory), but would appreciate others' thoughts.

Is it reasonable to envisage a resonance that is set up so that there is 
significant noise on power planes in the middle of an area that has no 
components, but has acceptable noise at the agents?  Perhaps you might see 
acceptable noise at the agents on the periphery of this area, but the noise 
from several agents adds up in the middle to an unacceptable level.  Common 
practice would be to only add caps at the agents.  If there is routing adjacent 
to the noisy power plane, that noise would be induced on that routing.

But, there are 2 (at least) possible problems:
1) no way to monitor the noise in the "bare" area between agents (at least 
easily)
2) no way to address the noise in the "bare" area between agents

These have led me to think that putting some empty cap sites in "bare" areas 
might be a good idea.  I haven't seen this particular problem, but 
investigating other noise issues led me to wonder...

Your thoughts?

Jeff Loyer

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of steve weir
Sent: Tuesday, September 23, 2008 2:12 PM
To: Joel Brown
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: bypass caps on unused pcb area

Joel, yes but not quite for the reason you state.  As long as the
capacitor distribution is not egregiously non uniform, AND ignoring
capacitance of attached ICs, then the bypass to plane cross-over
frequency depends on:

1. The mounted inductance of each capacitor
2. The capacitance per square inch of plane cavity, which is to say
225pF*eR/H ( H in mils )
3. The capacitor density per square inch

The two effects of leaving large unbypassed plane areas are:

1. The cross-over frequency comes down.
2. If the area has a long extent in one direction or another then modal
resonance can be worse which is unpleasant if it aligns to something
coherent like a clock or clock / 2.  The ways that cavities get excited:
a. An IC draws current through the cavity.
b. Signals inject into the cavity such as when a signal references the
top plane goes through a via and then references the bottom plane, or
signals cross moats.

Steve.
Joel Brown wrote:
> Is it a good idea to sprinkle bypass on areas of a pcb that are otherwised
> not used except for power / ground planes?
> The idea being to keep the power / ground planes from creating a resonance
> and radiating.
> Could such a resonace be exicted if there are no traces or components
> nearby?
> If so, how do we determine the interval of placement. We have no simulation
> tools to help us.
>
>
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