[SI-LIST] Re: bare die IBIS models

David

If the rise/fall time of the signals transitioning the "package" are long
compared to the "package" then you can zero out the package parasitics you
have in your base model.  When extracting the IBIS buffer model the SPICE
model should have accounted for all the effects of the die - stray C, etc.
in the signal path. What remains between your die model and the substrate
you are going to use is the bump itself and the return path in the chip.
There should be enough interlayer C in the power distribution layers that if
you have power/ground balls electrically close to the signal pins you can
assume the return path from the ground of the substrate to the ground in the
chip is a small path compared to the rise/fall time of the signals.  On the
other hand if the only ground on the chip is on the other side of the chip
you will have problems. Your results will depend on the geometries you have
in your application.

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065
503-430-1285 FAX
tom@xxxxxxxxxxxxx
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827 


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Tate, David
Sent: Wednesday, January 16, 2008 7:23 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] bare die IBIS models

I am using bare die (bumped flip chip) in a SIP application utilizing
solder attachment to the substrate.
I need to modify the package pin parasitic parameters in the
representative IBIS models. What should I use
if anything for the package pin patristic parameters for this type of
attachment?  I did find a document
that described a model which could be used for ACF attachment, but do
not know if the results would be the
same for solder attachment. The document is titled "High-Frequency SPICE
Model of Anisotropic Conductive Film
Flip-Chip Interconnections Based on a Genetic Algorithm" and appeared in
the IEEE TRANSACTIONS ON COMPONENTS
AND PACKAGING TECHNOLOGIES, VOL. 23, NO. 3, SEPTEMBER 2000.

best regards,

David Tate
Lockheed Martin Missiles and Fire Control
Senior Staff Circuit Design Engineer
Electrical Engineering - FPGA/Processor Design
E-Mail: david.tate@xxxxxxxx
 

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