[SI-LIST] about n-well parameters in standard 0.18um logic cmos process


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I have a question about the 'thickness' and 'conductivity' parameters of 
N-well in standard 2-well 0.18um CMOS Logic process, thanks! 

These two parameters are very critical for the performance of RF passive 
parameters. thanks again!

brief info will also be helpful!

 




Bi,Hai          

SJTU, Emlab

 

 



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