[SI-LIST] Xilinx Virtex2 driver spice models

Does anybody have experience with Xilinx Virtex2 I/O driver spice models
configured for 
LVDS in DDR-mode?  Their documentation gives clear recommendations regarding
the 
configuration signals (SELDx,SELTSx, etc), data and clock inputs, but they
say nothing 
about the tristate enable inputs (TS1IN and TS2IN) in Dual Data Rate mode.
(Replies 
from their spice help desk are not especially prompt either!)

Has anybody used these models and gotten them to run in LVDS+DDR mode?

jf

------------------------------------------------------------------------
"A home without a cat, and a well-fed, well-petted and properly revered
cat, may be the perfect home, perhaps, but how can it prove its title?"  
-Mark Twain

Jonathan Fasig                      Email:  fasig.jonathan@xxxxxxxx     
Mayo Foundation 
4001 41st Street NW 
MSC Sn 2-132                        Phone:  (507) 538-5464
Rochester, MN 55901                 Fax:    (507) 284-9171



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