[SI-LIST] Workshop on IC Failure Analysis / FIB

Dear All,
 

At Tessolve facility in Bangalore, India, we are arranging a Workshop on
Failure Analysis on IC.

Our aim is to present & demonstrate the process involved in Wafer Level VLSI
Circuit Edit through FIB.

 

 

Who should attend?

 

Engineers with the following background -

*       VLSI Design 
*       IC Test Engineering  
*       Hardware Design 
*       DFT
*       Failure Analysis
*       Process Engineering 

 

 

Program Dates:

 

The program is scheduled for September 22, 24 & 26 (1-day program that
repeats) from 09:00 to 17:00 hrs. 

The batch size is limited to 30 participants on each day as we need to go
through the demonstration of the process followed for Circuit Edit. 

The participation is WITH REGISTRATION ONLY and if there are more
registrations, we will repeat the program again in subsequent weeks.

 

 

For registration, the interested parties can send the following information:

 

*       Name of the participant
*       Company Name
*       Email ID
*       Contact No. (Phone/Cell)
*       Questions (if any) on Failure Analysis

 

 

We look forward to participation in this program in large numbers. 

For any additional information you may contact me at the below given contact
details.

 

 

With Best Regards.

 

T. N. Mohan

Business Development Manager

-------------------------------------------------------------------

Tessolve Services Pvt. Ltd.

Plot No. 31, Phase 2

Electronics City

Bangalore - 560 100, India.

-------------------------------------------------------------------

Phone    :  +91 80 4181 2500

DID        :  +91 80 4181 2566

Cell No.  :  +91 9900 206090

Email     :   <mailto:mohan.tn@xxxxxxxxxxxx> mohan.tn@xxxxxxxxxxxx

 

Fax        :  +91 80 4120 2626

URL       :   <http://www.tessolve.com> www.tessolve.com

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