[SI-LIST] Re: Why we need to use "Series resistor" at Transmitter?

Depends on how much the waveform slews into the loads. If the slew
rate is long enough and the interconnect short enough one would not
have to terminate. 

However, it is always wise to series terminate, it does not cost much
to do it and it will allow for migration to newer and faster parts
that may have to happen do to obsolence.

Bob

-----Original Message-----
From: Chan, Michael (Eng Hou) [mailto:Michael.Chan@xxxxxx]
Sent: Tuesday, October 29, 2002 11:28 AM
To: leeritchey@xxxxxxxxxxxxx; sandord@xxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Why we need to use "Series resistor" at
Transmitter?



I don't believe that statement is true. I have PCI bus that has 18 =
loadings on it and it is never terminated ( 33MHz ).

-----Original Message-----
From: Ritchey Lee [mailto:leeritchey@xxxxxxxxxxxxx]
Sent: Tuesday, October 29, 2002 10:18 AM
To: sandord@xxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Why we need to use "Series resistor" at
Transmitter?


The PCI bus, whick all PCs contain, is series terminated.  How many =
million of
those are there?  Just have to be careful when you clock data off the =
bus.

Lee

Sandor Daranyi wrote:

> > Jim,
> >=3D20
> > In regard to your comment: "Series termination
> > shoulkd NEVER be used wher the path is going to more
> > than one input i.e bus configuration.".  The ATA/IDE
> > interface used in PCs is series terminated at the
> > source and is bussed to two loads on data and
> > strobe lines.  The number of working systems in the
> > field is in the millions (every PC that has 2
> > drives).  The value of the series termination is a
> > great consideration (in ATA it is 22-50ohms).
> >=3D20
> > So series termination in busses can work.  Though, I
> > recommend a thorough understanding of the system
> > before employing this technique.
> >=3D20
> >=3D20
> > Charles Hill, consultant
>
> I concur.  In theory, I agree that it's not "nice", but I've seen =
series te=3D
> rminations (with no parallel termination at the far end) used =
successfull=3D
> y in designs where there were multiple inputs on a trace.  "Never" =
sounds=3D
>  neat but as with most good rules, there are exceptions.
>
> I also agree with the caveats.  In the examples I remember, the system =
was =3D
> running at a low clock frequency and all the inputs (not more than 3 =
in t=3D
> hat case) were close to each other at the end of a long trace.  It was =
of=3D
>  a daisy-chain topology, i.e. there were no branches on the trace, to =
min=3D
> imize the impedance discontinuities and reflections.  The inputs had =
high=3D
>  impedance.  Of course, one gotta think twice, even thrice, before =
doing =3D
> this on a clock signal.
>
> Sandor
>
> ---
> Sandor Daranyi
> Snr Design Engineer
> Aristocrat Technologies Australia
>
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