[SI-LIST] Re: Why we need to use "Series resistor" at Transmi tter?

I prefer not to use AC Termination for data lines. The termination
capacitance usually has to be a low value capacitance (good for edges).
Sometimes this value is not adequate for bursted data and the first rising
or falling edge after a prolonged high or low may be improperly terminated.
This can usually be seen as a poor ratty incident edge that misses a set-up
or hold-time at the receiver. Often, you lose the initial bit of a serial
data stream or you get an offset. Sometimes it will cause trouble on strobes
too.

Using AC termination on un-bursted clocks works okay except for long
multidrop clock distribution at high rates. Since the net continuously
changes states, the offset is minimized. 

I prefer to use series termination as much as possible (even in matched star
configurations) for the bulk of terminated nets. It is easy, power
efficient, and if well managed produces very quiet boards and reference
planes. Parallel and Parallel Thevenin are used for higher bandwidth nets
and where required (ECL, PECL, LVDS, etc). Sometimes route topology
management works well for terminating a net too.

As with all situations, the engineer should weigh options based on timing
and noise budgets with appropriate simulation.


Philip Ross Wellington
Mgr. Signal Integrity & EMI
L-3 Communications CSW


-----Original Message-----
From: Chris Cheng [mailto:chris.cheng@xxxxxxxxxxxx]
Sent: Wednesday, October 30, 2002 12:47 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Why we need to use "Series resistor" at Transmi
tter?



Not true again. Consider SSTL in DDR with both series and parallel
termination. 


-----Original Message-----
From: Jim Roberts [mailto:jgroberts@xxxxxxxxxx]
Sent: Wednesday, October 30, 2002 7:57 AM
To: Andrew.Ingraham@xxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Why we need to use "Series resistor" at
Transmitter?



Hi,
        Thanks Andrew.
        This has stimulated a good debate, but you are correct i should 
be more careful to give the conditions for the statement.

A series termination implies no termination at the Receive-end and therefore
full reflection dependent on resistive and capacitive parasitics.

These refections will cause an deflection of the rise and fall edges at the 
mid-point in the waveform, which is the threshold point for the receivnig
gate.
Therefore my indication of double clocking.
The amount is dependent on the rise time and the electrical distance from
the 
end of the line. [FR4 50ohm can give ~70ps/mm or ~140ps/mm for reflection]
If the rise time is bigger than the distance to the end of the line of
additional
inputs then you will have little problem; but for certainty SIMULATE
including
parasitics!!

Since the deterioration is an edge issue in the majority only clocks and
strobes
are at issue.

There is the alternative to terminate at the end [preferable].
Since many drivers can deliver the current in 50 ohms there is another
alternative
which is often used by me for processors:
AC-coupled (high-pass) end-termination.
The idea here is that it is only the high frequenies that need termination
for
performance [including emc]. So a series capacitor is chosen with the
terminate
rsistor that passes the necessary high frequency [0.35/Tr].
You will have reduced the current in the driver and maintained a good
waveshape.
Much success

Best Regards,
Jim
Remember: The driver impedance is nearly always more reactive than the
receiver
input(s) and therefore a less good place to terminate signals.

"Ingraham, Andrew" wrote:
> 
> Jim wrote:
> 
> > Series termination shoulkd NEVER be used wher the path is going to
> > more than
> > one input i.e bus configuration.
> > I have seen this happen in too many designs and the result of double
> > clocking
> > due to the non-monotonic edges of the clocks!!!
> 
> I suspect he meant to say that it should never be used WITH CLOCKS when
> going to more than one input.
> 
> Most non-clock data inputs can tolerate messy edges, and would be OK
> with plateaus and glitches ... as long as you do your timing analysis
> correctly!
> 
> However, such signals would spend some amount of time in an undefined
> state.  That's OK if the input gets clocked in at the right time by a
> state device.  If the input instead goes into a bunch of logic without
> being sampled, or if for some reason the input buffer itself is
> sensitive to time spent in an undefined state, then one should think
> twice before using series termination on a multi-drop bus.
> 
> As for PCI, it does use reflected waves, which means the drivers don't
> have a very low output impedance.  (If they did, we would say PCI uses
> incident wave switching.)  But PCI is usually not quite series
> terminated (in the sense of being matched) either.  The driver output
> impedance is lower than what would be ideal for series termination.
> It's a compromise, because drivers could be on the end or in the middle
> of a bus (cuts the effective Zo seen by the driver in half), and the
> stubs and loads tend to reduce the effective Zo as well.  So the drive
> strength is in the vicinity of 20 ohms.  Discrete series resistors
> generally should not be used with PCI, and can't be used on a plug-in
> card.
> 
> CPCI makes efficient use of discrete series resistors, which is part of
> what allows cPCI to have more slots per bus.
> 
> Regards,
> Andy
> 
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-- 
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           /___  ____ |  jrobert@xxxxxxxxxxxxxxxxxxxxx
 Jim      __  / /___/ /  jgroberts@xxxxxxxxxx
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