[SI-LIST] Re: Why is capacitor with high ESR

The reality will be the top/bottom layers will have microstrip signals added
(8 layers) which will force me to use ground plane reference and arrangement
like 6) with outer signal layers added will unlikely to happen in my design.
If you have microstrip signals and construct it with power as reference
plane at the bottom as in 6). You are in for more trouble than edge

-----Original Message-----
From: steve weir
To: Chris Cheng; Chris Cheng; ''sguzek@xxxxxxxxx ' '; ''Si-List ' '
Sent: 12/6/2004 10:38 AM
Subject: RE: [SI-LIST] Re: Why is capacitor with high ESR

Chris, I agree that 7 will work better than 5, although it might be a 
little bit less representative of what people actually build.

Where we disagree is whether 7 will actually be better than 6.  I don't 
think it will for the reasons stated.  Do you think you can convince
company to build two test boards, one as 7 and one as 6?  The
is to run models, assuming we want to trust them.



At 10:12 AM 12/6/2004 -0800, Chris Cheng wrote:
>I would think
>with the fence and sea of vias and decoupling in between will be better
>For 4) it is obvious there is no edge containment.
>For 5) while the edge containment can help the first five layers, the
>power plane can still have noise current which solely relie on
>caps that may or may not be effective and you will need a case like 6)
>ensure the complete edge containment (since you can short the gnd/power
>planes with vias).
>-----Original Message-----
>From: steve weir
>To: Chris Cheng; 'sguzek@xxxxxxxxx '; 'Si-List '
>Sent: 12/5/2004 11:30 PM
>Subject: RE: [SI-LIST] Re: Why is capacitor with high ESR
>No, I don't see a lot of value from the very low R's in existing
>caps.  Yes, lots of ground vias do divide the cavities up and cause a
>of scattering.  Unfortunately, even a good number of those vias rise to
>surface to meet decoupling caps which then become a source of
>radiation.  This is not to mention the other signal vias that do the
>We could have some fun constructing some ML boards with a stackup
>least two ground planes one close to each end of the stack-up that
>for a fence.  We could add more layers, but I think the following 6
>is adequate for the thought-problem / experiment:
>1.  Oscillator with nice fast CMOS drivers in the middle as our noise
>source, aside from local decoupling in the middle of the board, it will
>an open cavity.
>2.  Same as 1. but with ground fence only at the board edges.
>3.  Same as 1. but with fence using DET with the best dissipative caps
>we can get.
>4.  Same as 1, but with lots of ground  and power vias distributed
>the board many connecting to decoupling caps on the surface.
>5.  Save as 4, but with fence as in 2.
>6.  Same as 4, but with DET as in 3.
>I believe that we agree that between 1, 2, and 3, that 3 will have the
>lowest radiation.
>I believe that we agree that between 1 and 4, 2 and 5, and 3 and 6,
>will have lower radiation than 1/2/3 respectively.
>What I think you will find interesting is that of 4, 5, and 6, that 6
>offers considerable improvement over both 4 and 5.  This has been the
>subject of much of Istvan's work on the benefits of DET.  The impinging
>energy only hits the vias once on its way out to the board edge where
>absorbed.  The "ice-cube trays" of 4. help to remove a lot of the
>from the noise, but we are pretty much stuck with the dielectric losses
>dump the HF energy into heat.  What does not become heat escapes on its
>to Zontar.
>I hope that we can agree that an alternative demonstration is to break
>the Vcc plane into sections that are tied together with lossy
>networks.  Would you be surprised to find that the EMC performance of
>a board with a thick cavity is much better than the same geometry board
>where the Vcc has not been divided, sic 1, or 4 from above?
>At 10:41 PM 12/5/2004 -0800, Chris Cheng wrote:
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