[SI-LIST] Re: What will happen when short the SERDES IO to GND?

Richard:
 
   Thanks for the technical reply on Christmas holiday. Have a good holiday!
 
   It looks the major concern related with hot-swap compliance is the short 
current reliability, correct?
 
Thanks,
Neo
 
--- On Wed, 12/24/08, Ward, Richard <richard.ward@xxxxxx> wrote:


From: Ward, Richard <richard.ward@xxxxxx>
Subject: [SI-LIST] Re: What will happen when short the SERDES IO to GND?
To: "neoflash2008@xxxxxxxxx" <neoflash2008@xxxxxxxxx>, "steve weir" 
<weirsi@xxxxxxxxxx>, "liuluping 41830" <liuluping@xxxxxxxxxx>
Cc: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>, "wangyongjin@xxxxxxxxxx" 
<wangyongjin@xxxxxxxxxx>
Date: Wednesday, December 24, 2008, 3:13 PM


Hi Neo,
I guess the ability or need to use circuit tricks depends on your specific 
requirements and applications. Most of my work is around ~10G CML applications 
where the short characteristics are between the local supply/gnd and high-speed 
nodes - which is relatively controlled. Other applications may have short 
options to non-signal supplies, much more tricky. I notice USB 2.0 proposed to 
remove the signal to 5V VBUS short Hot Swap requirement partly to save Si 
area/power for the 5V tolerance.

For the 10G field, some rules (I, t) do exist (e.g. OIF CEI Driver Short 
Circuit Current).

The basic problem is the trade-off between placing enough metal down on Si to 
meet the EM rules for a short (signal-signal or signal-supply) based on the 
max. current in that condition and the time you want to withstand. Naturally, 
this is the worst place to put extra metal and together with the low-R path for 
ESD is a fine balance between output cap and performance. Some applications 
will allow short-time current handling only (say 100us) - but we tend to go for 
the full "lifetime" to cover EM and put the metal down, but if you are 
designing for a specific application - I'd get the current and time 
requirements clarified as early as possible and see how it affects metal widths 
for your process, based on your shorted driver circuit.

Regards,
Richard

________________________________
From: Neo [mailto:neoflash2008@xxxxxxxxx]
Sent: 23 December 2008 01:03
To: steve weir; liuluping 41830; Ward, Richard
Cc: si-list@xxxxxxxxxxxxx; wangyongjin@xxxxxxxxxx
Subject: Re: [SI-LIST] Re: What will happen when short the SERDES IO to GND?

Richard:

   I'm instersted in "the hot plug protection rules".

   For a CML type TX driver of a serial transceiver, what kind of circuit 
tricks shall we take to be compliant with hot plug rules?

Regards,
Neo

--- On Thu, 7/10/08, Ward, Richard <richard.ward@xxxxxx> wrote:
From: Ward, Richard <richard.ward@xxxxxx>
Subject: [SI-LIST] Re: What will happen when short the SERDES IO to GND?
To: "steve weir" <weirsi@xxxxxxxxxx>, "liuluping 41830" <liuluping@xxxxxxxxxx>
Cc: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>, "wangyongjin@xxxxxxxxxx" 
<wangyongjin@xxxxxxxxxx>
Date: Thursday, July 10, 2008, 5:12 AM

As Steve says - it depends.



Many XAUI style output drivers use majority passive termination to positive
supply. By connecting the output nods to gnd you'll be bypassing the

curre
nt control stage and starve it.



Most nodes should survive with the (usually) 50 Ohms between rails for shor
t times. Most will meet the hot plug protection rules. Long times on smalle
r feature sizes could permanently damage the die due to the high electro-mi
gration. Depends on the design/linewidths. ESD doesn't tend to catch these


events unless spikes at insertion/removal occur as well. But assumed you me
ant a DC short.



"short" or "terminate"? - big difference naturally.



Short will likely kill the signals, risks damage over time, terminate will 
likely give collapsed swing at best.



Regards,

Richard



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