[SI-LIST] Re: What is the limit?

Hello, Uday,

It is not so much a question of "capacity" of memory or other resources, but
more a question of how long you are willing to wait for the simulation to
run.  A general purpose analog simulator doing full-chip transistor-level
analysis is normally reserved for simulating critical paths (whether analog
and/or digital), rather than entire chips.  There have probably been some
benchmarks published - try Google.

A related issue is the availability of a field solver for chip-level SI
parameters in a format compatible with the selected simulator.  This would
include the resistance and capacitance of the epi/well/substrate layers, as
well as inductance and capacitance for high-speed traces, along with
capacitive (and possibly inductive) coupling.

- Lynne

Dr. Lynne Green 
Greenstreak Programs


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Udaysekhar Anumalachetty
Sent: Wednesday, March 31, 2004 4:25 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] What is the limit?

Dear SI gurus,
I do not have much experience in the SI field.

I need to evaluate the industry standard spice tools
(hspice,eldo,smartspice,.. etc)

Has anybody done a full chip spice transistor level
simulation capacity analysis on these tools with the
following parameters:

1) Capacity in terms of number of gates/cells

2) No crosstalk included

3) Transient analysis

Thank you for your comments
Uday A

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