[SI-LIST] Re: What is the frequency range of the Stratix III cor e

Steve, Alexandre,
I guess the most helpful information would be to know the amount of 
on-package core
capacitance and the cumulative inductance of the package's core path and 
also the
expected maximum core-current fluctuation...

Regards,
Istvan




steve weir wrote:
> Alexandre, in order to properly design the core PDN you need to know the 
> device parasitics.  Once the package to PCB inductance becomes limiting, 
> there is little to nothing that the PCB can do to further improve power 
> delivery to the die.
>
> In order for Tr of the core to be a serious board design issue the core 
> has to have grossly inadequate local storage.  The Stratix III does not 
> suffer that problem. 
>
> Steve.
> Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx wrote:
>   
>> Steve, 
>>
>> Mon problème n'est pas du pouvoir(de la puissance), mais de la gamme de 
>> fréquence.
>> Pour l'entrée-sortie de découplage, je suis ok et j'utilise l'expert de 
>> pouvoir(puissance) Altera, Pour "la Tension Fondamentale" j'ai utilisé aussi 
>> ces outils pour le pouvoir(la puissance).
>> Mais je n'ai aucune information sur le temps de hausse de signal fondamental 
>> ?
>>
>> Je veux maintenir(entretenir) la cible impedance de DC à 0.35/Trise.
>> Donc je ne sais(connais) pas comment définir la fréquence de découplage 
>> maximale.
>>
>> Merci pour votre aide
>>
>> Alexandre AMEDEO
>>
>>  
>>
>> -----Message d'origine-----
>> De : steve weir [mailto:weirsi@xxxxxxxxxx]
>> Envoyé : mercredi 23 avril 2008 16:19
>> À : Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx
>> Cc : si-list@xxxxxxxxxxxxx
>> Objet : Re: [SI-LIST] What is the frequency range of the Stratix III
>> core
>>
>>
>> Alexandre, Altera has a power planning tool that is part of Quartus.  
>> For impedance you will need to estimate the number of resources that you 
>> will be using and their switching frequency.  Alternatively, the 
>> estimator will evaluate a completed design.  To get the details of the 
>> component parasitics you need to talk to Altera.
>>
>> Steve.
>> Alexandre.AMEDEO@xxxxxxxxxxxxxxxxxx wrote:
>>   
>>     
>>> Hi everybody,=20
>>>
>>> I try to define the Power distribution System for the core voltage of a
>>> Stratix III,
>>> but I don't know how to define the Frequency Target. The datasheet =
>>> doesn't
>>> specify the rise time of the core Clock.
>>> I have just the frequency of the core.
>>>
>>> I work with Power Integrity from Cadence.=20
>>> The target impedance is the same for all the frequencies, is it ok?
>>> Some people speak about adaptative target impedance (the current is
>>> decreased with frequency thus the target impedance is increased)?=20
>>> Is there a formula to define target impedance with F dependency, Z(f)?  =
>>>
>>>
>>> If anybody has some information about this two points,=20
>>> Thank you for all your answers
>>>
>>> Alexandre AMEDEO
>>>
>>>
>>>
>>>
>>> -----Message d'origine-----
>>> De : si-list-bounce@xxxxxxxxxxxxx
>>> [mailto:si-list-bounce@xxxxxxxxxxxxx]De la part de navaram kumar
>>> Envoy=E9 : mercredi 23 avril 2008 15:10
>>> =C0 : si-list@xxxxxxxxxxxxx
>>> Objet : [SI-LIST] How to do optimization for minimum power delay =
>>> product
>>>
>>>
>>> Hi
>>> How to do optimization for minimum powerdelay product.
>>> Can anybody give me some idea where to start
>>> Thanks& Regards
>>> K.Navaram Kumar
>>>
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>>>   
>>>     
>>>       
>>   
>>     
>
>
>   



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