[SI-LIST] Re: What do you do when the manufacturer's model doesn't match the measurements?
- From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 30 Aug 2010 09:29:53 +0200
Hello Iain,
for SI simulations we usually do die to die. In this case it is good to
have a seperate package model of the DRAM. I do not really trust the RLC
IBIS package modeling, but for DDR2-800 it should not be that bad.
For high speed the reflection that you see at the pin can be very
strong, but for DDR2-800 I would not expect that the difference between
pad and pin would cause a Ringback with double crossing.
I guess when you simulated at the die you just disabled the Package in
the IBIS and used the RLC values to model this seperate, correct ?
One question would be if you are working on a small or a large system ?
in a system with just a single rank, short routing and a high controller
slew rate this effect will be worse compared to a highly loaded system
with slow slew rates.
We did several correlations with DDR2 and DDR3 and have been quite
successfull to correlate simulation with measurement. This was work for
Qimonda, so we have been sure to have accurate DRAM die and package
models. The Controller model was the biggest source of concern
Another question is, which IBIS you do not trust:: The CPU driver or the
DRAM receiver (incl. ODT), or the DRAM package part of the DRAM IBIS.
Simplest way to check your simulation is to replace both models with an
ideal resistive driver and an ideal Termination. If you still see the
reflection at the pin it has nothing to do with the Driver and receiver
IBIS models, but it needs to be somewhere else in the simulation.
Regards
Hermann
EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
Veilchenstrasse 1
94554 Moos
Tel.: +49 (0)9938 / 902 083
Mobile: +49 (0)176 / 787 787 77
Fax: +49 (0)3212 / 121 9008
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of Iain Waugh
> Sent: Friday, August 27, 2010 3:00 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] What do you do when the manufacturer's model doesn't match
> the measurements?
>
> Hi all, please can you advise!
>
> Our aim is to prove the vendors' IBIS models on a dev board so we can have
> confidence that simulations of our own 400MHz DDR2 design (using the same
> parts) will be accurate. We're simulating with Hyperlynx 8.0 and have taken
> the most up-to-date IBIS models from the vendors' websites.
>
> We've made a pretty good free-form schematic model of the dev board with the
> target CPU and memories (plus 'scope probe at the receiver's pin). The
> initial simulations were horrible with a massively non-monotonic rising edge
> crossing the Vil and Vih levels of the receiver twice. We used a 6GHz LeCroy
> 'scope with 1GHz probes to measure the actual dev board's signal integrity
> and the edges were clean.
>
> In my mind, that proves that I can't trust the model. The catch, however, is
> that the vendor then told us to put the simulation probes at the die instead
> of at the pin. We re-simulated and the non-monotonic edges went away - they
> actually looked like the measurement!
>
> Would you trust the results of a simulation when the measured case only
> correlates with a simulation having probes in a different place? Can we use
> the wrong (but matching) model to guide us to the best routing topology? I'm
> tempted to just use standard good SI practises and ignore the simulations.
>
> Best regards,
>
> Iain Waugh
>
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