[SI-LIST] Re: What do you do when the manufacturer's model doesn't match the measurements?

  • From: "Lance Wang" <lwang@xxxxxxxxxx>
  • To: "'Iain Waugh'" <iwaugh_pub@xxxxxxxxxxxxxxx>
  • Date: Fri, 27 Aug 2010 10:32:20 -0400

Steve has very good comments about measurement correlations with
simulations. 

For models self (not only IBIS models), many models are out there without
correlations/validations (sad to say that many IBIS models are). I think
this is one reason why you would like to correlate by yourself before trust
them for the simulations. 

You can ask the vendor to see if they have validated models in some ways.
Some vendors have the validation report handy but you will have to ask.
These reports will give you some info about validation results and test load
settings. It could help you to figure out if you have mistakes with your
measurement settings too. 

Hope this helps,

Lance Wang
IO Methodology Inc.

SIMDE - The most complete IBIS modeling and validation tool.
www.iometh.com/Product/SIMDE

 
 


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of steve weir
Sent: Friday, August 27, 2010 9:34 AM
To: Iain Waugh
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: What do you do when the manufacturer's model doesn't
match the measurements?

No, you should never make assumptions about correlation that you haven't 
verified.  For sanity check you should set-up probes in the simulation 
that match the PCB, and then compare the results.  Ideally the probes 
you set-up will be located such that they are meaningful with respect to 
what the die sees, which is what you really care about. 

There are many ways to go wrong in each the simulation and measurement.  
In your case, I think your scope probe bandwidth is woefully 
inadequate.  For DDR2, 2GHz is about the absolute minimum floor I would 
consider measuring and then with substantial adjustment for the limited 
bandwidth.  5GHz scope plus probe bandwidth would be a lot preferable.  
You need to really understand the parasitics in your probing.  
Hopefully, you included that in your modeling.  Finally, you want to be 
sure that your scope measurements don't suffer DSP spongiform 
encephalopathy.

Steve.
Iain Waugh wrote:
> Hi all, please can you advise!
>
> Our aim is to prove the vendors' IBIS models on a dev board so we can have
confidence that simulations of our own 400MHz DDR2 design (using the same
parts) will be accurate.  We're simulating with Hyperlynx 8.0 and have taken
the most up-to-date IBIS models from the vendors' websites.
>
> We've made a pretty good free-form schematic model of the dev board with
the target CPU and memories (plus 'scope probe at the receiver's pin).  The
initial simulations were horrible with a massively non-monotonic rising edge
crossing the Vil and Vih levels of the receiver twice.  We used a 6GHz
LeCroy 'scope with 1GHz probes to measure the actual dev board's signal
integrity and the edges were clean.
>
> In my mind, that proves that I can't trust the model.  The catch, however,
is that the vendor then told us to put the simulation probes at the die
instead of at the pin.  We re-simulated and the non-monotonic edges went
away - they actually looked like the measurement!
>
> Would you trust the results of a simulation when the measured case only
correlates with a simulation having probes in a different place?  Can we use
the wrong (but matching) model to guide us to the best routing topology?
I'm tempted to just use standard good SI practises and ignore the
simulations.
>
> Best regards,
>
> Iain Waugh
>
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-- 
Steve Weir
IPBLOX, LLC 
150 N. Center St. #211
Reno, NV  89501 
www.ipblox.com

(775) 299-4236 Business
(866) 675-4630 Toll-free
(707) 780-1951 Fax


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