[SI-LIST] Re: V-level of LVDS jitter measurement

Hello.



I would suggest to improve your jitter performance by changing the layout
and or the power circuit around the LVDS VCO or oscillator.  Noise in the
ground or power is getting into your oscillator and causing AM or FM modulation
which causes excessive jitter.  Noise can also be injected thru the air. 

I have seen it before on line receiver circuits, sample clock circuits and
oscillators, QPSK, up to 64QAM modulator/demod designs.



Power to the oscillator has to be real quiet as well as the ground under it. I
would suggest try to power up the VCO circuit with a battery and then measure
the jitter. This will tell us if the power is causing it.  Another
solution is to make a peninsula for the ground under the oscillator. This will
make the noise that is potentially in the ground steer clear of the
oscillator.  Is the oscillator in or near the center of the board? This could 
be another problem. Cut a C shape in the ground and put the oscillator inside 
the C shape.  This is a very effective trick as well. Its actually one of the 
first things I tried years ago in a design and worked very effectively. 



These are some of my tricks in lowering jitter and phase noise. Another thing 
to try if you have a frequency synthesizer is to simply remove the oscillator 
and inject the right frequency into the circuit with the appropriate buffer and 
then measure the jitter to see how much layout, power or grounding is effecting 
the performance.  Taking a design that is marginal is an iterative step by step 
process.  

The light ( flouorescent or incandescent ) that is eminating from the bench 
above the circuit can also inject noise into your VCO and increase jitter. Take 
a look around and see what is near it that can induce noise ! 



Richard Jungert

160 pcb designs and mods

2 us patents.

http://www.rjungert.com

> Date: Fri, 13 Mar 2009 11:27:40 -0700
> From: jory_mckinley@xxxxxxxxx
> Subject: [SI-LIST] Re: V-level of LVDS  jitter measurement
> To: james.f.peterson@xxxxxxxxxxxxx; james.f.peterson@xxxxxxxxxxxxx
> 
> Hello Jim,
> You may want to AC couple the measurement if the design calls for it.  This 
> will place your trigger at 0V.  Depending on the type of jitter (DJ) you are 
> seeing check the power/ground planes feeding the clock for excessive noise as 
> well as any other reference point(s) feeding the clock.  
> -Jory
> 
> 
> 
> 
> ________________________________
> From: "Peterson, James F (EHCOE)" <james.f.peterson@xxxxxxxxxxxxx>
> To: si-list@xxxxxxxxxxxxx
> Sent: Thursday, March 12, 2009 3:41:57 PM
> Subject: [SI-LIST] V-level of LVDS  jitter measurement 
> 
> SI experts,
> 
> We are trying to make a careful jitter measurement of an LVDS clock.
> It's a SERDES reference clock running at about 50MHz. 
> 
> We are seeing way more jitter than expected. The trigger point right now
> looks like it is at the cross point of the diff signals (vdiff = 0v).
> Shouldn't that be changed to around 50mv or 100mv?
> 
> Thanks in advance.
> Jim Peterson
> Honeywell
> 
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