[SI-LIST] Re: V-level of LVDS jitter measurement

Hello Jim,
You may want to AC couple the measurement if the design calls for it.  This 
will place your trigger at 0V.  Depending on the type of jitter (DJ) you are 
seeing check the power/ground planes feeding the clock for excessive noise as 
well as any other reference point(s) feeding the clock.  
-Jory




________________________________
From: "Peterson, James F (EHCOE)" <james.f.peterson@xxxxxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Sent: Thursday, March 12, 2009 3:41:57 PM
Subject: [SI-LIST] V-level of LVDS  jitter measurement 

SI experts,

We are trying to make a careful jitter measurement of an LVDS clock.
It's a SERDES reference clock running at about 50MHz. 

We are seeing way more jitter than expected. The trigger point right now
looks like it is at the cross point of the diff signals (vdiff = 0v).
Shouldn't that be changed to around 50mv or 100mv?

Thanks in advance.
Jim Peterson
Honeywell

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