[SI-LIST] V-level of LVDS jitter measurement

SI experts,

We are trying to make a careful jitter measurement of an LVDS clock.
It's a SERDES reference clock running at about 50MHz. 

We are seeing way more jitter than expected. The trigger point right now
looks like it is at the cross point of the diff signals (vdiff = 0v).
Shouldn't that be changed to around 50mv or 100mv?

Thanks in advance.
Jim Peterson
Honeywell

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