[SI-LIST] Re: Via model

Dorin,

The first thing you have to decide is: what frequency range do you
want/need to simulate.  A !0ps delay Tline has a quarter-wave
resonance at 25GHz.  You may need to include this frequency
in your simulation range only if your bit rate is 5Gbps or higher,
or if you make detailed studies of the interconnects.

The DC convergence problem usually occurs when you try
to simulate silicon together with short line segments.  One
option is to simulate the interconnects first, without the
silicon, to find out what details you can safely leave out to
simplify your model while keeping the required accuracy.

Regards,
Istvan


----- Original Message -----
From: "Dorin" <dorin.oprea@xxxxxxxxxxx>
To: "Istvan NOVAK" <istvan.novak@xxxxxxxxxxxxxxxx>
Cc: "si-list" <si-list@xxxxxxxxxxxxx>
Sent: Thursday, November 27, 2003 10:33 AM
Subject: [SI-LIST] Re: Via model


> Thanks for your feedback; this model is quite ingenious.
> The problem I face with my particular circuit when using very short TL
> (<10ps) is that hspice complains about dc convergence failure.
> Do you have any particular option I can try?
> gmindc is asking for is 0.1 which I think is too big ....
> Cheers,
> Dorin
>
>
>
> Istvan NOVAK wrote:
>
> > Dorin,
> >
> > Both the PI and T equivalent circuits of vias are just approximations,
> > therefore they should be used only in cases when the signal edge
> > passing through the model is significantly longer than the delay of the
> > model, which is sqrt(L*C); in that case the two models should give
> > very closely the same waveforms.
> >
> > If your application calls for fast
> > edges, where this condition cannot be met, a more detailed via
> > model is needed.  In the most generic case, where you have 1...N
> > metal layers in the PCB, and the trace transitions from layer A to
> > layer B, you may need a PI circuit formed of three transmission lines.
> > All three transmission lines can be low loss or loss less.  Two
> > open-ended transmission lines replace the capacitors in your present
> > PI circuit, and the third line connects the two shunt lines and replaces
> > L in your PI circuit.  By adjusting the Zo and tpd values of all three
> > transmission lines independently, you can capture the via stub
> > resonances separately on top and bottom, include pad capacitances,
> >  as well as the delay and capacitive or inductive nature of the portion
> > of the via barrel between layers X and Y.
> >
> > Regards,
> >
> > Istvan Novak
> > SUN Microsystems
> >
> > ----- Original Message -----
> > From: "Dorin" <dorin.oprea@xxxxxxxxxxx>
> > To: "si-list" <si-list@xxxxxxxxxxxxx>
> > Sent: Thursday, November 27, 2003 9:06 AM
> > Subject: [SI-LIST] Via model
> >
> > > Hi,
> > > What should be the model for the via:
> > > a) C/2 to gnd - L - C/2 to gnd or
> > > b) L/2 - C to gnd - L/2
> > > The circuit I simulate shows a significant difference between the two
> > > cases.
> > >
> > > Thanks,
> > > Dorin
> > >
> > >
> > >
> > >
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