[SI-LIST] Re: Via Structure
- From: "Alexander Ippich" <Alexander.Ippich@xxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 19 Apr 2012 16:34:59 +0200
Hi Marc-Andre,
this is very strange. I would never substitute a round via capture pad with a
square pad from a manufacturers point of view. Enlarging the diameter helps
preventing break out of via, but as a rule of thumb, we all like nice rounded
structures, not pointed corners.
There is no real issue with the square pad (we use them on all the SMD pads
anyway), but I do not see how it would possibly help with the yield.
One question, what data format did you use to transmit the data? Was it a more
advanced format like extended Gerber or ODB++ or was it simple Gerber with a
separate wheel file? In case of the separate wheel, there is a possibility that
during setting up the aperture table, somebody just accidentially typed a "S"
(as in square pad) instead of a "R" (as in round pad). And this is all it takes
to convert a round pad into a square one by accident.
Best regards,
alex
_______________________________________________________________
Alexander Ippich
Sr. Signal Integrity Engineer
Multilayer Technology GmbH & Co. KG
Herrenberger Strasse 110
71034 Boeblingen - Germany
Phone +49 7031 211 3375
Fax +49 7031 211 5309
Email alexander.ippich@xxxxxxxxxxxxx
Pers. haftender Gesellschafter: Multilayer Technology Geschäftsführungs GmbH,
Geschäftsführer: Werner Widmann
Sitz der Gesellschaft: Böblingen, Amtsgericht Böblingen HRA242264
http://www.multek.com
Endless innovation creates changes for tomorrow
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Filion, Marc-Andre
Sent: Thursday, April 19, 2012 4:15 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Via Structure
Hi,
We had a funny surprise when we received the bare pcb of a prototype. The PCB
fab changed the via pad from a typical round shape to an enlarged square one.
It tickle our mind and came to a quick conclusion that it won't affect much the
signal integrity.
My question here is: Is this a more effective way to build PCB (in term of
yield)? Is there any pitfall related to this technique?
best regards,
Marc-André Filion, Eng | Hardware designer | Kontron Canada | T 450 437 5682
x2243 | E marc-andre.filion@xxxxxxxxxxxxxx
<mailto:marc-andre.filion@xxxxxxxxxxxxxx>
Kontron Canada Inc
4555 Rue Ambroise-Lafortune
Boisbriand (Québec) J7H 0A4
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