[SI-LIST] Re: Validation of XTK results for clock skews

Suchitha

First off try setting your timestep to 0.002.
If that works then this is whats is going on.

I presuming that this 7.6" is not one long straight piece of
copper. If you look in the .top file the chances of seeing 

NET CLOCK
NODE U1 1
NEXT 7.6 ... (where 7.6 is your overall net length 
               in one straight piece of etch)
NODE U2 1  
;

is highly unlikely.
More likely you'll see for example
NODE U1 1
NEXT 0.3 ... ( 0.3 is the length of the segment)
..
NEXT 0.9 ...
...
NEXT 1.2 ...
...
NODE U2 1

;
where the number following the 
NEXT statment represents the length
of each trace segment on your board. This is
what I mean by segment length. It should 
correspond one to one with
how the physical etch is actually routed on your board.
If you expect accurate flight times on traces
with traces segments as small as 10 mils for example you'd
need to set the timestep down to 
Tpd/1000 * 10. Given Tpd ~ 2 ns/ ft. then the time step should
be set to 0.002. If you expect to accurately 
measure delays with the cursor in the Waveviewer, 
you should do likewise for the Display step.
Just keep in mind that if you save or export the
waveforms you could end up with very large files with 
delay step set at a small value.

Hope that helps. Let me know if this
solved your problem.

Marc

> -----Original Message-----
> From: Suchitha.V@xxxxxxxxxx [mailto:Suchitha.V@xxxxxxxxxx]
> Sent: Thursday, June 21, 2001 2:30 AM
> To: mhumphreys@xxxxxxxxxxxx
> Cc: si-list@xxxxxxxxxxxxx
> Subject: Re: Validation of XTK results for clock skews
> 
> 
> 
> 
> Hello Marc,
> 
> Thanks for your reply.
> I have a few clarifications wrt your reply,
> 
> a)What is meant by shortest etch segment? In my case, the 
> total length of the
> clock is about 7.6" from clock synthesizer pin to the
>    CHIPSET_CLOCK pin and from clock synthesizer pin to the  
> CPU_CLOCK pin.
> b) The  FR4 i'm using  has an Er=3.9. The time step i have 
> taken in the
> parameter option in XTK is 0.1ns.
> 
> 
> Looking forward to your reply,
> 
> Thanks & Regards
> Suchitha
> ------------------------------
> 
> From: Marc Humphreys <mhumphreys@xxxxxxxxxxxx>
> Subject: [SI-LIST] Re: Validation of XTK results for clock skews
> Date: Tue, 19 Jun 2001 09:59:33 -0400
> 
> 
> Suchitha
> 
> On point b)
> 
> > b) Why is there a large difference between simulated and
> > practical results?
> 
> Check that your timestep is smaller than
> the flight time along your shortest etch segment.
> What you'll get for a flight time
> if this is not the case, is a minumum of
> (time step) x (number of segments).
> eg 10 segment 0.1 inches long, whith time step
> of 0.1ns = 1 ns. It should be more like .16ns.
> 
> The other biggest factor would be inaccurate
> Dielectric constant. Check with your board vendor
> what value to use. FR4 for example can
> be as low as 3.6 depeneding on resin content.
> 
> Marc
> 
> -----------------------------------------------------------------
> Marc Humphreys
> Axiowave Networks, Inc
> Marlborough, MA
> (508) 460-6969
> -----------------------------------------------------------------
> 
> 
> > -----Original Message-----
> > From: Suchitha.V@xxxxxxxxxx [mailto:Suchitha.V@xxxxxxxxxx]
> > Sent: Tuesday, June 19, 2001 12:14 AM
> > To: si-list@xxxxxxxxxxxxx
> > Cc: si-list@xxxxxxxxxxxxxxxxx
> > Subject: [SI-LIST] Validation of XTK results for clock skews
> >
> >
> >
> >
> >
> >
> > Hello all,
> >
> > This question is related to validation of clock skews from
> > XTK with practical
> > clock skews measured on board.
> > I am interested in the clock skew between the CPU_CLOCK and
> > the CHIPSET_CLOCK.
> > Practically, the skew has been measured on the CRO at the
> > destination of the
> > CPU_CLOCK pin and the CHIPSET_CLOCK pin.
> > From XTK, I have measured the flight time for the CPU_CLOCK
> > (i.e the delay from
> > the clock syntheziser pin to the CPU_CLOCK pin), and the
> > flight time for the
> > CHIPSET_CLOCK (i.e, the delay from the clock synthesizer pin to the
> > CHIPSET_CLOCK pin).
> > I have calculated the clock skew to be the difference between the
> > Tflight(CPU_CLOCK) and the Tflight(CHIPSET_CLOCK).
> > The flight times have been calculated using the typical
> > corner. The simulated
> > clock skew is nowhere close to the practical skews measured.
> > The simulated clock
> > skews are from the board file. The skews have also been
> > calculated for the fast
> > and slow corners.
> >
> > I would like to know,
> > a) What are the parameters i need to take into for
> > calculating the simulated
> > clock skews from XTK?
> > b) Why is there a large difference between simulated and
> > practical results?
> > c) How do i measure the clock skew from XTK?
> > d) Is the procedure i have followed for calculating the clock
> > skew from XTK
> > correct?
> >
> > Looking forward to your valued suggestions and help.
> >
> >
> > Thanks and Regards,
> > Suchitha
> 
> 
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