[SI-LIST] Re: VIA-FillingMaterial
- From: Graham Kus <nemisonic@xxxxxxxxx>
- To: johny leon <leonjony@xxxxxxxxx>
- Date: Wed, 6 Apr 2011 19:30:30 -0400
Hi Johny,
I agree with Steve about using a simulation tool to analyze your results. We
use Sigrity's PowerDC tool to analyze DC metrics such as current density and
IR drop for our boards and SoC packaging. We use data from this tool to
justify an increase of our via plating when necessary (increase via plating
thickness) which was cheaper than paying for conductive via fill. It also
shows IR drop and current-density effects of copper thickness and via count
in the PCB or SoC packaging.
Another important impact on ampacity or DC performance is to realize there
are 2 via types available for board designs. There is an old style via
called "thermal relief via" which is not appropriate for power regulators or
SoCs. This is constructed with an "X" shape of copper connecting the via to
the plane(s). This provides thermal relief between the via and the heat-sink
action of a plane(s). Conversely, a solid via will connect the entire
annular ring to the plane and provides maximal heat sinking to the plane(s).
When dealing with thermal issues, there is a JEDEC standard for measuring
thermal performance (JESD51-9) that might shed some light
on ancillary problem of thermal performance if you are talking about an SoC.
Here is a simple web-based calculator for your information dealing with
Ampacity. You can increase the plating thickness such that it amounts to a
solid-fill via.
http://www.circuitcalculator.com/wordpress/2006/03/12/pcb-via-calculator/
<http://www.circuitcalculator.com/wordpress/2006/03/12/pcb-via-calculator/>
-Graham
On Mon, Mar 28, 2011 at 2:22 AM, johny leon <leonjony@xxxxxxxxx> wrote:
> Experts ,
>
> Need an advice about VIA filling methods.
>
> I would like to use VIA filling using 'Solid Cu' for through hole, hidden
> and Micro VIAs thinking that that would increase the current carrying
> ability and connectivity to the planes/tracks. Is this correct?
>
> My board is a high current board ,upto 150A, but for short duration. This
> board gets power through , through-hole VIAs from BOT Layter and transfer it
> to TOP Layer components(8Layers). FYI: This is not a high speed board.
>
> I thought of providing Solid Cu filling instead of non-conductive fill for
> VIAs thinking that would enable VIAs to carry 'current' effectlively. But
> I'm not sure about the manufacutrability and other aspects of Solid Cu
> filling of the VIAs. I wanted to fill the following VIAs with Cu :
> uVia - L1 TO L2 and L8 to L7
> Hidden and stacked with the above VIA - L2 to L7
> Hidden VIA - L2 to L7
>
> So my questions are :
> 1. Is Solid Cu filling of VIAs good method compared to non-conductive fill?
> 2. Conductive fill means Cu fill or PCB Manufactures use any other
> materials?
> 3. Are there any other methods , other than Conductive filling of VIAs, to
> enable VIAs to conduct heat and 'current' effectively
> 4. Finally, Is Solid Cu filling a good method???
>
> Thanks in advance,
> Johny.
>
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