[SI-LIST] Re: Using Load Switching FETs
- From: steve weir <weirsi@xxxxxxxxxx>
- To: otter30@xxxxxxxxxxxxx,<si-list@xxxxxxxxxxxxx>
- Date: Mon, 26 Mar 2007 07:12:21 -0700
Jim, Yes, using power FET's has similar bypass issues to POL
converters. For each voltage node you need to maintain impedance
within an acceptable range throughout the frequency range that loads
draw power from it. A power FET can isolate a node inductively, even
though the DC resistance remains quite low. The bypass capacitors,
power cavity(s), and bypass within the individual IC packages are
what carry the load above the point where jwL exceeds
Ztarget. Whether you need bypass capacitor(s) for a node depends on
what you have on it.
Steve.
At 11:27 PM 3/25/2007, Jim Hall wrote:
>Hello,
>
>Does anyone have any thoughts on using load switching FETs between a main
>power plane
>and a local power plane devoted to 1 or 2 ICs?
>
>Some of the PFETs offered these days feature Rds values below .01 ohm and
>package para-
>sitic inductances of a nH or so. For situations where one has many ICs with
>multiple
>voltage supplies that have to be sequenced on in a particular order, the
>FETs seem very
>attractive. I realize that for fast ICs with large dI/dt needs, the
>parasitic L could be
>a bottle neck. But can this not be compensated for with a properly chosen
>array of de-
>coupling caps, and would the same issue not exist for point of load
>regulator modules?
>
>Any advice would be appreciated.
>
>Thanks,
>Jim
>
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