[SI-LIST] Update on Pulse Research Lab clock divider sample

From: "Tang, George" <George.Tang@xxxxxxxx>
To: "SI-List" <si-list@xxxxxxxxxxxxx>
Date: Wed, 11 Jan 2006 00:07:19 -0700
All, 
 

About a month ago, Steven Kan from Pulse Research Lab sent out an email
requesting someone to test the performance of their sample clock
divider.  I volunteered for the task.  Now the testing is done, so I
think I should give an update to those who are interested.  

 

This clock divider box has the capability of doing 2^n (n: 1,2,3...6)
divisions.  I tested the device for its operating bandwidth and jitter
performance and was pleasantly surprised by my measurements.  Steven in
his email claimed that the device has a simulated bandwidth up to 12GHz,
and my measurements show that its actual bandwidth goes out to 14GHz.  I
thought that was very good margin.  But what really impressed me was the
jitter performance.  I fed in a clock source with 170fs one sigma RJ,
and the clock divider puts out a divided down clock with 770fs one sigma
RJ.  That is surprisingly good for a small device with such high
bandwidth.  Usually you would expect this kind of performance from a
device weighing 40 lb and takes up a whole lot of bench top space, but
this clock divider is small enough to fit in your pocket.  I have the
measured plots if you are interested in seeing them.  Send me an email
offline and I'll get them to you.  

 

I normally use clock dividers to generate clean clock sources.  If you
have worked with frequency generators you would know that the jitter
performance of a frequency generator output is not constant across its
frequency range.  A typical frequency generator may put out 3.8ps one
sigma RJ at 100MHz, but at 2GHz, it only has 1.1ps one sigma RJ.  If you
use this jittery 100MHz clock source to drive your PLL circuit to try to
meet the Sonnet or Fibre Channel spec, you would have a very difficult
time.  But if you set the frequency generator to 3.2GHz and use the
clock divider to do a 'divide-by-32' you can get a very clean clock
source that is worth 20 ~ 30 thousand dollars (if you were to buy
another variable frequency clean clock reference).   Another use for a
clock divider would be to phase-lock your SerDes receiver to your bench
top Bit-Error-Rate-Tester (BERT) machine, but your PLL reference-clock
input is 100MHz while your BERT puts out a 6.4Gbps data and 6.4GHz
clock.  This clock divider can easily perform the interfacing and
dividing task for this application.  There are many uses for this
device, but I can only name a few for now.  

 

 

By the way, this is definitely not a sales AD, and please do not contact
me for pricing.  

 

 

Regards, 

 

George 

 


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[SI-LIST] Update on Pulse Research Lab clock divider sample

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