If you are talking about fast edges I/O, I will take a proper reference plane to signal over any decoupling (plane, under package caps or whatever) any day. And I don't think external decoupling has anything to do with fixing SSO problem. I have no idea about what you are referring to as "it is very tough to make the circuit stable at high speeds" can you explain ? -----Original Message----- From: Lee Ritchey [mailto:leeritchey@xxxxxxxxxxxxx] Sent: Tuesday, August 12, 2003 9:25 AM To: si-list@xxxxxxxxxxxxx; Vishram Pandit Subject: [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator Ah! The key here is double sided PCBs. That means no plane capacitor, which a part of the UMR test. Problem with double sided PCBs is the absence of planes to tie things together. This does make EMI with fast edge parts very difficult, if not impossible to control. In this case, capacitor placement does matter because there is a great deal of inductance in the power path due to the lack of planes. As part of this, it is very tough to make the circuit stable at high speeds, as well. When we tried to make NICs using double sided PCBs at 3COM for fast Ethernet, we had this very problem. Just barely worked. When we added encryption, didn't work at all. Too many data lines switching simultaneously. Lee Lee Ritchey leeritchey@xxxxxxxxxxxxx Why Wait? Move to EarthLink. ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu