[SI-LIST] Re: Turn on oscillation power analysis
- From: pwelling@xxxxxxxxxxxxxx
- To: Raymond.Anderson@xxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Mon, 25 Mar 2002 13:06:31 -0700
Jeffrey,
I had this happen on a project as well. The frequency was 834 MHz - pretty
slow these days. The coupling mechanism was caused by the high AC Collector
current coupled into the supply rail. The AC current looped back through the
Collector - Base resistor path creating the oscillation. I found 2 ways to
correct it:
1) Put a ferrite bead over the Base lead of the transistor - limited the
bandwidth for intended signal too.
2) Added high frequency decoupling at the collector to provide a preferred
path for the AC current to go. This was the best solution.
While my problem was discrete, and yours is a chip problem (higher FTs),
decoupling or providing a preferred return path may correct the problem. You
may want to look at the ground path for the emitter resistor too (maybe
additional vias to limit inductance). The value of Collector - Base resistor
may be examined as well, lower values may pump more AC current into the
Base.
Parasitics are much different, but sometimes the return path is worth
examining (layers above or below the layer).
Hope this helps.
Philip Ross Wellington
Mgr. Signal Integrity & EMI
L-3 Communications CSW
-----Original Message-----
From: Ray Anderson [mailto:Raymond.Anderson@xxxxxxx]
Sent: Friday, March 22, 2002 10:58 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Turn on oscillation power analysis
Jeffrey-
What is the approximate frequency of oscillation (i.e. is it low freq
or in the UHF range ?) As Mike pointed out, emitter followers, though
we usually think of them as a stable topology with a gain <1, actually
can be problematic due to parasitics causing instability at freqs
> 1 GHz.
-Ray
>
>Jeffrey,
>
>I understand that you primary concern is oscillation itself and how to
quell
>it.
>Is your transistor hooked up as emitter follower? Because if yes, then
>e-followers are prone to oscillation around unity gain frequency and one
way
>of quelling it is a capacitance from Base to Collector.
>
>Mike.
>
>-----Original Message-----
>From: Merwin Jeffrey-GJM002 [mailto:Jeffrey.Merwin@xxxxxxxxxxxx]
>Sent: Friday, March 22, 2002 10:55 AM
>To: 'si-list@xxxxxxxxxxxxx'
>Subject: [SI-LIST] Turn on oscillation power analysis
>
>
>
>I have a PNP pass transistor that was originally designed to act as a
switch
>turning on from a DC supply into a downstream primarily capacitive load.
The
>charge current is limited by the Beta of the PNP switch device.
>
>A die shrink occurred in the part and some of the devices began to fail.
>Doing a DC worse case analysis there is no reason for the failure however
>the device now oscillates at turn on. While the envelope of power
dissipated
>in the device is no higher than the original non-oscillating design a
>question exists as to whether the full area of the die is still being used
>or if only a small portion is being used due to the oscillation.
>
>Does anyone no how to determine how the current will crowd around the
>emitter in a device when an RF current is present?
>
>How much of the current will be flowing in each area of the die?
>
>And how to quantify this to be used in a worse case analysis?
>
>Thanks for any help you can give me
>
>
>
>Jeff Merwin
>Principle staff engineer
>Motorola
>gjm002@xxxxxxxxxxxxx
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