[SI-LIST] Re: Trace Width @ 3Gb/s
- From: Bob Patel <whizplayer@xxxxxxxxx>
- To: rsterner@xxxxxxxx
- Date: Mon, 10 Jun 2002 09:47:22 -0700 (PDT)
Hi! Rudy,
As you mentioned in the data pattern the error happens
on the first transition from 0 to 1 after 3
consecutive bits of 0 and does not happen on the
second transition. Also, your link is AC coupled.
I don't know if you tried this already but
1) Change your data pattern to 010101, like a clock
and see if you get any error.
2) Next if you don't get error with the above pattern
then change the pattern back to original and use DC
coupled link. Remove AC coupling.
The problem could also be that the receiver cannot
hanfle the DC drift with the consecutive run's of 0 in
tha pattern and the EYE at the receiver is closing.
What is the value of AC caps and what are their
characteristics?
Good luck
Bob
> -----Original Message-----
> From: Rudy Sterner [mailto:rsterner@xxxxxxxx]
> Sent: Monday, June 10, 2002 9:28 AM
> To: si-list@xxxxxxxxxxxxx; Hassan O. Ali
> Subject: [SI-LIST] Re: Trace Width @ 3Gb/s
>
>
>
> Hello,
>
> The error occurs in the following type of
> pattern: '0001010'.
> It is at the first '1'. The signal is NRZ. We
> observed it on
> the scope and noticed that the pulse resulting from
> the
> first '010' transitions was smaller than the second
> pulse which
> explains the error.
>
> As for the dimensions: We buried the traces
> between two
> ground planes. We used 4-mil width, 7-mil spacing,
> half-oz.
> copper. Distance from trace to ground plane is 5
> mils. The
> signals are AC coupled. The individual trace
> impedance is
> higher than 50 Ohms; however we control both the
> driver
> and receiver impedance. Neither seemed to help in
> this case.
>
> For the next round, we are going to run these
> traces on the outer
> layer to minimize the effects of vias.
>
> Regards
>
>
> Rudy Sterner
>
>
> ----- Original Message -----
> From: "Hassan O. Ali" <hassan@xxxxxxxx>
> To: "Rudy Sterner" <rsterner@xxxxxxxx>;
> <si-list@xxxxxxxxxxxxx>
> Sent: Monday, June 10, 2002 9:00 AM
> Subject: Re: [SI-LIST] Trace Width @ 3Gb/s
>
>
> > Rudy,
> >
> > Could you be specific on the kind of issues you
> have with the SerDes link?
> That way you
> > can receive suggestions that are more specific to
> your situation.
> >
> > Yes, 4-mil tracks can be a problem. With those
> tracks, in a microstrip
> format you need
> > less than 3-mil height to achieve close to 50-ohm
> single-ended line
> impedance (which
> > might be your goal). With that small height and at
> that data rate,
> component pads
> > (especially AC-coupling cap pads, if you have any)
> start to dominate
> heavily causing
> > tremendous impedance discontinuities.
> >
> > In addition, narrow tracks give rise to higher
> loss - both line-loss and
> reflection loss
> > due to pronounced discontinuities at various
> locations (the connector
> launch-point is
> > one of the most important ones).
> >
> > Regards.
> >
> > Hassan.
> >
> >
> >
> >
> >
> > On Jun 10, "Rudy Sterner" <rsterner@xxxxxxxx>
> wrote:
> > >
> > > Hello,
> > >
> > > We have some issues with a SerDes which we
> think
> > > may be related to the trace width on the serial
> line. The
> > > serial port is a differential pair passing data
> at 3 Gb/s.
> > > The trace width is 4 mils. Length is
> approximately 5 inches.
> > > The differential impedance is 100 Ohms. Other
> information
> > > which may be of use is the board material is
> FR-4 with an
> > > Er of 3.9. It is specified at this data rate.
> > >
> > > My question is: Are the traces too narrow?
> Should I
> > > expect better performance with 8-mil traces?
> > >
> > > Thank You
> > >
> > > Rudy Sterner
> > > LSI Logic
> > >
> >
> >
>
>
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