# [SI-LIST] Re: Trace Width @ 3Gb/s

• From: "Zabinski, Patrick J." <zabinski.patrick@xxxxxxxx>
• To: si-list@xxxxxxxxxxxxx
• Date: Mon, 10 Jun 2002 11:41:01 -0500

```Rudy,

My guess is that your question stems from a problem you're
experiencing with bit error rate (BER).  The question then
becomes one of what influences BER.  In my view, BER
is directly related to signal to noise ratio (SNR).  In
communication texts,

BER = Q(SNR)

Q is a non-linear function, and tools like MatLab
and Mathematica (Erfc) provide it in various forms.

By reducing line loss (by widening the trace), you will
increase SNR, which will improve BER.  This is good.

The question becomes how much can you practically improve
your BER through lower-loss, or if you're too far in the
mud to do anything useful.

For example, here's a chart showing how much improvement
you can make in effective BER by increasing the received
signal strength by 5% (i.e., very small change):

Baseline        Improved        Delta-Improvement
1E-18           1E-20           100X
1E-12           1E-13           10X
1E-6            1E-6            1.1X

Where:
Baseline is the BER measured of the baseline system
before you do anything
Improved is the BER after you've increased the
received signal strength by just 5% (!!!)
by increasing the trace width (while keeping
the noise the same)
Delta-Improvement is the relative improvement in BER

As you can see, if your deep in the mud with BERs down
around 1E-6 (or worse), a slight change in trace width
is not likely to do you much good.  You should probably look
at noise sources and ways of improving noise.

If your baseline BER is pretty- to almost-good, then a
tweak of trace width will help.

Note: in looking at BER, Q, and SNR, a 5% change
in signal strength is equivalen to a 5% change
in noise level.  Point being, in addition to looking
at ways of reducing signal loss, you might consider
looking at ways of reducing noise (e.g., signal
filtering, power supply decoupling, signal isolation,
etc.).

Hope this helps,
Pat

> Hello,
>
>    We have some issues with a SerDes which we think
> may be related to the trace width on the serial line.  The
> serial  port is a differential pair passing data at 3 Gb/s.
> The trace width is 4 mils.  Length is approximately 5 inches.
> The differential impedance is 100 Ohms.  Other information
> which may be of use is the board material is FR-4 with an Er
> of 3.9.  It is specified at this data rate.
>
>   My question is:  Are the traces too narrow?  Should I
> expect better performance with 8-mil traces?
>
> Thank You
>
> Rudy Sterner
> LSI Logic
>
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