[SI-LIST] Re: Trace Spacing Rule

Hi Kevin
Both Howard Johnson's book "High Speed Digital Design" and Lee Ritchey's 
book "Right the First Time" discuss cross talk in some detail and how to 
determine the % coupling between traces.  In the end it has to do with 
your noise budget on the signals and how much cross talk you are willing 
to tolerate.   Tools such as Hyperlynx can simulate the cross talk based 
on various factors such as driver IBIS model, parallel length, trace 
separation, PCB stack up, etc.   Based on your ground bounce budget (PDN 
impedance, signal reflections, logic levels, etc) you can determine  how 
much cross talk your system can tolerate before you risk violating the 
logic lows/highs, min/max voltages of your ICs. 

The main determining factor in crosstalk as far as your question goes 
would be to use 3h, or three time the height over the reference plane. 
Using Lee Ritchey's book for instance for a center stripline, at h=10 
mils, the % coupling at 5 mils separation is about 19%, using 3h the 
coupling would be 1%.   In reducing the maximum coupling for cross talk, 
decreasing the separation of your signal layer relative to their reference 
planes is a good starting point. 

My main area of expertise is designing for EMC, and we are not involved in 
anything other than CMOS logic levels here on boards, so take what I say 
with a grain of salt.  But either of the previously mentioned books will 
help you calculate and determine what is the ideal spacing/height for your 
application.

Erin McPhalen

Hardware Designer
R&D Hardware
SCHNEIDER ELECTRIC
Victoria,BC, Canada




Kevin K <khai77069@xxxxxxxxx> 
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[SI-LIST] Trace Spacing Rule






Hi All,
What's the real rule of thumb for trace spacing? 
I have seen 3w (w = trace width) and also 3h (h =
height of trace above reference plane).  I'm
interested in 100 Ohm diff pairs. 

Thank you,
Kevin


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