[SI-LIST] Re: Tools to Create IBIS Models

In a message dated 3/21/2004 10:37:43 AM Pacific Standard Time, 
scott@xxxxxxxxxxxxx writes:
If a Spice model is created with impropper assumptions or by leaving out 
important elements of the circuits (like ESD structures) it will not be 
very accurate.  IBIS models, on the other hand, can be created directly 
from measurement and are as accurate as the measurements we take.  
Teraspeed Labs  has measurement based IBIS models that accurately 
reflect the device operation.  With full process corner silicon, we have 
developed models which are more accurate than the original Spice models 
(as reported by our customers, the IC vendors themselves.)
**************
Scott:

You are right on target re: ESD structures. I have found the clamping 
networks (or lack of inclusion of their affects in the IBIS models) are a very 
common 
source of error. It is these very networks that contribute the maximum 
variation of driver and receiver output/input capacitance as a function of 
signal 
voltage, which in turn alter the rising and falling edges of the signals. That 
is one of the key elements in my paper.

Some of your comments raised my eyebrows a bit..."IBIS models, on the other 
hand, can be created directly from measurement and are as accurate as the 
measurements we take.  
Teraspeed Labs  has measurement based IBIS models that accurately reflect the 
device operation....and..." If you want to know if your IBIS model is 
accurate, do the same, or create it directly from measurements, as we do."

I have seen and appreciated your modeling work (which IMHO was reflected in 
one of the best papers at DesignCon 2004), but I am puzzled as to how one would 
extrapolate lab measurements to models that correctly reflect/predict the 
corners of silicon processes. I would think that any reasonable number of 
measurements on real devices would still fall within the one-sigma range of 
performance. I have used model parameter extrapolations (based on historically 
documented process tolerances supplied by cooperative silicon vendors) for very 
critical modeling applications, but there is always some inherent error risk in 
those extrapolations. I also found that my clients were initially reluctant to 
add 
compensating design margins (with its attendant cost impact) when such 
extrapolations were not confirmed by room ambient lab tests. (But they 
ultimately 
agreed because of the criticality of their application.) 

Respectfully,

Mike

Michael L. Conn
Owner/Principal Consultant
Mikon Consulting

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