[SI-LIST] Re: Timing analysis
- From: "ariazi" <ariazi@xxxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 20 Dec 2005 14:09:21 -0800
=20
> Can you please guide me in performing post layout timing analysis.
>How to calculate hold time, setup time , setup margin, hold margin =
from
the simulated=20
>wave form. (what is the formulas used).
=20
=20
Dear Si-List Members:
First, I would like to wish all of you a great Holiday season!
Indeed, timing computation are quite important. SI analyses =
frequently
involve evaluation of both signal quality and timing margins. However,
signal quality degradations can be=20
tolerated in many cases provided they do not cause timing violations.
Timing analyses of a high-speed net usually requires taking into
consideration driver and receiver chips timing specifications. These IC
specs are of two types: (1) timing requirements, and (2) guaranteed
responses. Among timing requirements (constraints) are setup time, hold
time, and pulse width. A typical guaranteed response is chip's =
propagation
delay. Constraints normally have either a maximum or minimum (but not =
both)
unlike delays which almost always contain both minimum and maximum =
values.
One of my previous postings on the si-list, (subject: Common Clock and
Source Synchronous=20
Timing Margins; Date: January 20, 2002) contains several references, a
listing of timing parameters plus formulas for setup and hold margins.
The driver/receiver ICs Technology, the bus Topology (plus loading), =
and
Termination can significantly impact timing. For a high-speed bus, the
clock skew and jitter may noticeably influence the effective clock =
period
and timing margins.
It is useful to note that some of the parameters required for timing
margins are obtainable from manufacturer data sheets, while other =
parameters
need to be ascertained via simulations (post-route or pre-route). For
instance, the minimum and=20
maximum flight times are extracted by means of simulations while driver =
Tco,
receiver Tsetup, Thold from devices' data sheets.
Timing specs furnished by manufacturers data sheets are based on test =
loads
which=20
usually differ from system interconnect loading. Consequently, the =
flight
time values resulting from system simulations need certain adjustments
before they can be accurately applied in computation of timing margins.
Timing diagrams which label the times between signal transitions/edges
provide a popular means=20
to clarify timing specifications. Timing equations can be derived from
timing diagrams and then
summarized in a spreadsheet (such as Excel) or a table. An article =
entitled
"DDR2 Design Guide For Two-DIMM Systems" (TN-47-01 available on Micron =
Web
Site) presents several examples of=20
timing budgets in table format. That paper also discusses concept of
"derating"; heavy system loading can lead to derating of setup and hold
times (given by data sheets) depending on slew rates.
Based on timing relationships between a data signal and a clock, one =
way
to enhace setup margin
is to shorten the data trace length (or increase clock trace length) at =
the
price of lowering
the hold margin. Conversely, hold margin can be improved by lengthening =
the
data line or shortening
clock trace (but at expense of setup margin). An alternative way to
increase setup margin is by
incresing the clock period (lowering operation frequency) and this will =
not
affect hold margin.
Merry Christmas and Happy New Year!
Abe Riazi
ServerWorks
=20
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