[SI-LIST] Re: Timing analysis
- From: "Istvan Nagy" <buenos@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>, <jennifer.maharani@xxxxxxxxx>, "Gregory R Edlund" <gedlund@xxxxxxxxxx>
- Date: Mon, 1 Jun 2009 18:30:26 +0100
Greg,
There is another type of interface, which is still commonly used, the
"asynchronous" interface.
Microcontrollers and DSPs have their local buses this type. You didn't
mention it here, also not in your book. Using strobe signals (write, read,
ALE) to latch the data. Even on high-performance computer boards with
Core2Duo processor on them we have a uC to FPGA interface for the IPMI
subsystem, or DSPs running on 750MHz core, they have a 133MHz asynchronous
local bus for peripheral and flash. The timing is similar to the
synchronous, but a littlebit different. Check my timing calculator about it:
http://www.buenos.extra.hu/iromanyok/PCB_Timing_analysis.xls , or a
datasheet:
http://www.analog.com/en/embedded-processing-dsp/blackfin/adsp-bf533/processors/product.html
And I think the most fun, is to design the board and -not an ASIC but- the
FPGA/CPLD code too (for a peripheral residing on the bus), all by yourself.
This happens at our site very often.
Istvan Nagy
Concurrent Technologies, UK
----- Original Message -----
From: "Gregory R Edlund" <gedlund@xxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>; <jennifer.maharani@xxxxxxxxx>
Sent: Monday, June 01, 2009 3:51 PM
Subject: [SI-LIST] Timing analysis
> Jenni,
> Since you're asking about the fundamentals, maybe it would help to have a
> little background philosophy on the topic (from my own perspective, of
> course).
>
> The way I see it, a very simplified version of our job description as
> Signal Integrity engineers could read like this: make sure the data that
> came from the transmitting chip is safely stored in the receiving chip. In
> that sense, what we do is a lot like what chip designers do when they run
> timing analysis (agree with Istvan).
>
> There are two general design scenarios:
> 1. The chips are already defined and you have specs for them (probably the
> most common)
> 2. You're working with an ASIC development group on a new chip (we do this
> a lot at IBM)
>
> Scenario 2 is more fun! You get to see inside the chip and maybe even
> inside the circuits. Scenario 1 can be more challenging because the
> constraints can be more rigid.
>
> Both scenarios can involve either industry standard specifications or
> nonstandard specs. With the industry standard specs, you will have to
> think about how your part of the link fits into the spec. For example, if
> you are designing only a PCIe expansion card, you don't need to worry
> about the system board. This is a different way of thinking than if you
> know the exact chips that will reside on both ends of the interface.
>
> There are three general speed categories:
> 1. common clock (slowest)
> 2. source synchronous (next fastest, data and clock travel from TX to RX
> together)
> 3. high-speed serial (fastest, receiving chip generates high-speed clock
> from slower reference clock and positions it relative to data)
>
> In category 3, all the nasty effects (crosstalk, losses, etc) tend to get
> mushed together, and you can't tolerate very much of any of them. In
> categories 1 and 2, it's easier to see exactly how the signal effects
> detract from your timing margin because they're running slower.
>
> In all three cases, there is always a latch somewhere sampling the data,
> and you have to pay attention to setup and hold of that latch at various
> levels of abstraction.
>
> I hope that helped set the stage. I'd be glad to answer a question or
> two.
>
> Good luck to you.
>
> Greg
>
> Greg Edlund
> Senior Engineer
> Signal Integrity and System Timing
> IBM Systems & Technology Group
> 3605 Hwy. 52 N Bldg 050-2
> Rochester, MN 55901
>
>
> Msg: #1 in digest
> From: Jennifer Maharani <jennifer.maharani@xxxxxxxxx>
> Subject: [SI-LIST] Timing analysis
> Date: Thu, 28 May 2009 08:32:12 +0200
>
> Dear experts,
>
> What is timing analysis?
> What do I need to compare e.g. data, strobe ?
> Is there any book or article explaining the procedure in detail?
>
> Many thanks,
> Jenni
>
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