[SI-LIST] Re: Tightly coupled VS loosely coupled diff pairs

  • From: "Greim, Michael" <mgreim@xxxxxxxxxxxx>
  • To: "'cheard@xxxxxxxxxx'" <cheard@xxxxxxxxxx>, MikonCons@xxxxxxx,si-list@xxxxxxxxxxxxx
  • Date: Wed, 12 Sep 2001 09:11:24 -0400

Hi All,

I've seen the arguments for counterboring as well,
and while they are intriguing from an electrical 
perspective are they really practical from a recurring
manufacturing perspective?  In the concept you would
be applying stress to the via wall during the counter
bore process and then leave the bored via exposed.
Now wouldn't that leave exposed copper and the chance
of the via wall delaminating from the fr4?

I would think that a sequential lam blind via would offer
you the same benefits with greater reliability.  With a 
5G board one will probably be looking at semi-exotic 
materials so perhaps the cost premium for this technology
might be tolerable.

Comments?

MG 

-----Original Message-----
From: Heard, Chris [mailto:cheard@xxxxxxxxxx]
Sent: Monday, September 10, 2001 9:07 PM
To: MikonCons@xxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Tightly coupled VS loosely coupled diff pairs



Mike,

Can you comment on the effect on pcb thickness and therefore plated =
through
hole capacitance of running broadside coupled?  Thickness certainly
increases which drives capacitance up which can dominate connector Zo
matching.  Is this more significant a problem than localized =
differences in
Er and glass/resin?  There are some companies talking about =
"counterboring"
plated through holes to virtually eliminate capacitance in order to get =
into
the 5Gb range.

What is your recommendation for dealing with these negative effects?

Thanks,
Chris

-----Original Message-----
From: MikonCons@xxxxxxx [mailto:MikonCons@xxxxxxx]
Sent: Monday, September 10, 2001 6:30 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Tightly coupled VS loosely coupled diff pairs



Hi, Lee. I have added this response to the SI list to perhaps hear of =
others

experiences on the topic.
****
You asked, "Do you have some analytical evidence that tight coupling is =

better?=A0 All of the analysis I have done shows that tight coupling =
actually=20
reduces signal quality, specifically edge rate and jitter.

This becomes prominent at 2.5 GB/S.

I'd be interested in some analysis that shows what the benefir of tight =

coupling is."
****

I have been on the road for the last month, and will continue to be so =
for
at=20
least four more weeks; therefore, my comments are brief. The abrupt =
answer
to=20
your inquiry is "Yes, absolutely." A longer answer follows.

For the last three years, I have redesigned non-functional, =
loosely-coupled=20
designs, and designed multiple original, tightly-coupled designs (both=20
backplanes and line cards) for new, upcoming 3G systems for multiple=20
companies, including Nokia and CacheFlow. I am dealing with 50 ps rise =
times

and 2.5 to 5 GBPS systems.

As I'm sure you are aware, edge rate degradation for any line =
configuration=20
is partially dependent on the losses of the harmonics of the =
fundamental.=20
That degradation is universal and must be dealt with in all designs.
However,=20
a potentially greater impact on edge rate occurs because of different =
delays

of the signal propagation on each of the two traces of a differential =
pair.=20
The edge rate degradation is 1/2 the difference in propagation delays=20
(originating from whatever source). Closer routing (and therefore =
tighter=20
coupling) of traces minimizes this delta in two ways; viz, minimization =
of=20
physical length differences and different effective dielectric values =
caused

by localized glass-resin variations in the core and pre-preg layups. =
More=20
tightly coupled traces minimize both effects. Note that the localized=20
variations in effective dielectric constant are near impossible to =
model,=20
even for one board vendor with a known material source and a given =
stackup.=20
These variations will vary from board to board even within one lot.

Another major contributor in edge rate degradation is non-symmetrical=20
coupling to adajent signal traces and pins in connector pin fields. =
Contrary

to recommendations made by another well-known consultant for AMP HS-3=20
connectors, I have conclusively demonstrated superior eye diagram
performance=20
of pairs that bracket the signal pin rows, as opposed to the ground pin
rows.=20
This comment is particularly applicable to CML designs (like for =
Vitesse=20
parts) as opposed to complimentary, but single-ended, drivers (like the =
IBM=20
DASL line). This degradation effect can also be encountered when dual=20
stripline construction includes short parallel segments near the trace =
pair,

but on the adjacent layer.

Still two other (perhaps obvious to you, but not to many SI analysists) =

degradation mechanisms are encountered because of assymmetrical rise =
and
fall=20
times of complimentary outputs, and different clock-to-output delays =
(skew)=20
of the complimentary driver outputs.

And, yes, I have modeled and analytically correlated ALL of the above
effects=20
with real hardware designs. Most of these analyses were performed and =
are=20
parts of proprietary, cutting-edge reports to my clients; therefore, I =
have=20
not publicly published my findings for consumption by the SI community. =
As I

TRY to back off from a busy consulting schedule, I plan to update and =
expand

my own earlier seminar and publish two or three papers on this subject.

Respectfully,

Mike

Michael L. Conn
Owner/Principal Consultant
Mikon Consulting
(408)727-5697

=A0=A0=A0 =A0=A0=A0 =A0=A0=A0*** Serving Your Needs with technical =
Excellence ***

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