[SI-LIST] Re: The maximum length of a bus?

Jack,

I have the book but I haven't finished it.
I believe you are looking at the question at point of view of "Timing".
The timing issue of RGMII interface is tricky. It is specified as the
following:

For Version 1.0
                                                            min    typ
max
----------------------------------------------------------------------------
-
The data to clock skew at transmitter -0.5     0      0.5
The data to clock skew at receiver       1.0     1.8    2.6

The clock trace need extra 1.5n~2.0ns delay routing on the PCB.

For Version 2.0
Some chip vendors build Delay Lock Loop in their chip to compensate timing
to reduce PCB space.
The specification is:
                                                            min    typ
max
----------------------------------------------------------------------------
Setup time at transmitter                       1.2   2.0
Hold time at transmitter                        1.2   2.0
Setup time at receiver                           1.0   2.0
Hold time at receiver                            1.0   2.0


Beyond the timing issue, what else should I consider about?

Regards,


C.Y. Cheng



----- Original Message -----
From: "Jack W.C. Lin" <JackWCLin@xxxxxxxxxxxx>
To: <cycheng@xxxxxxxxxxxxxx>
Sent: Monday, October 28, 2002 9:41 AM
Subject: RE: [SI-LIST] The maximum length of a bus?


> Hi C.Y.:
> Please write down the total clock path and time it takes. Please also
write
> down the total signal path of the bus and time it takes. The constraint is
> the total time of clock should be larger than the signal. Then you will
get
> the maximum length of the signal. Please be noted that the buffer delay
> (i.e. T_co )should take into account. You can reference the book called"
> High Speed Digital System Design" which was wroten by 3 Intel guys.
> Jack
>
> -----Original Message-----
> From: C.Y. Cheng [mailto:cycheng@xxxxxxxxxxxxxx]
> Sent: Monday, October 28, 2002 9:14 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] The maximum length of a bus?
>
>
> Good day gurus,
>
> I have been asked a question,"What is the maximum length of RGMII
interface
> that your chip can drive?"  We know that RGMII interface is a chip to chip
> bus, all the data synchronous to the clock of the driver. Rise time of
clock
> is 0.75ns(20%-80%). Both edges of the reference clocks drives data at
> 125MHz. Maximum length specified in the specification is 6 inches, but in
> some application cases bus length would be more than 6 inches.
>
> How do I model/analysis the bus to find the answer?
>
> Regards,
>
>
> C.Y. Cheng
> System design Engineer
> Realtek Semiconductor Inc.
>
>
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