[SI-LIST] Re: The Implications of Nonmonotonic Transitions

You may also end up getting glitches at the output of your receiver. Most 
receivers will have some hystersis built in to handle nonmonotonic transitions, 
but depending on the width and depth of the nonmonotonic transition and the 
slew rate (slower transitions are worse) the reciever may end up with a false 
transition at the output. This may happen even if the signal did not go down 
all the way to Vil(max).

Snehamay

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of tucsonAz
Sent: Tuesday, January 20, 2009 10:17 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] The Implications of Nonmonotonic Transitions

I have a nonmonotonic transition on a processor¢s data line.

Example:
On a rising edge the signal passes the Vih(min), then back below it, and then 
again back above Vih(min). Termination may not be possible due to packaging 
constraints and the vendor will most likely only endorse an ideal square wave.

The timing concern is that this ringing from a reflection would push into the 
setup time. However, the signal is stable before the required setup time of the 
interface, therefore, no impact.

The signal integrity concern is that does this nonmonotonic transition have any 
impact to the LVCMOS (not sstl) at the receiving end? Even though the signal is 
an acceptable high voltage at the setup time.

I have looked back through my device physics books from school attempting to 
find what impacts nonmonotonic transitions present to CMOS with no success. I 
have done web searches only finding papers talking about the results on the 
timing margin or leading into termination techniques.

Are nonmonotonic transitions acceptable to CMOS outside of setup times?  Can 
anyone suggest further reading sources?

Your help is appreciated,
Joe Engineer


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