[SI-LIST] Re: The Implications of Nonmonotonic Transitions

Hello, Joe,

Some possible concerns:
* SETUP TIME!  Depending on the timing and strength of the non-monotonicity,
this could INCREASE required setup time.  The datasheet setup time assumes
a monotonic switching input.  <I have seen this in my I/O design
experience.>
* Probable increase in crosstalk, with potential to cause faults on other
signals.  
* Likewise, probable increase in power consumption.  And EMI.

Only simulation can tell you how serious these effects are.  An SI simulator
can
check for crosstalk effects (amplitude and timing shifts).  A SPICE tool
with the
transistor-level receiver netlist can simulate the effect of the
non-monotonicity
on setup time.

Best of luck.

Lynne

PS: CMOS logic has no failure mode that I am aware of with non-monotonicity.



"IBIS training when you need it, where you need it."

Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@xxxxxxxxxxxxxx


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of tucsonAz
Sent: Tuesday, January 20, 2009 8:17 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] The Implications of Nonmonotonic Transitions

I have a nonmonotonic transition on a processor¢s data line.  
 
Example: 
On a rising edge the signal passes the Vih(min), then back below it, and
then again back above Vih(min). Termination may not be possible due to
packaging constraints and the vendor will most likely only endorse an ideal
square wave.  
 
The timing concern is that this ringing from a reflection would push into
the setup time. However, the signal is stable before the required setup time
of the interface, therefore, no impact.
 
The signal integrity concern is that does this nonmonotonic transition have
any impact to the LVCMOS (not sstl) at the receiving end? Even though the
signal is an acceptable high voltage at the setup time.
 
I have looked back through my device physics books from school attempting to
find what impacts nonmonotonic transitions present to CMOS with no success.
I have done web searches only finding papers talking about the results on
the timing margin or leading into termination techniques.
 
Are nonmonotonic transitions acceptable to CMOS outside of setup times?  Can
anyone suggest further reading sources?
 
Your help is appreciated,
Joe Engineer

   

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