[SI-LIST] Re: TDR impedance measurement and rise time
- From: "Istvan Nagy" <buenos@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 7 Apr 2009 21:34:26 +0100
Hi
Peter from LeCroy wrote:
"short impedance discontinuities... if you limit the frequency content ...,
the bumps get smeared out by the slower risetime and they don't look so bad"
- i think for these Test Coupon measurements is the point not to measure a
real PCB trace with the lots of discontinuities, but to get the impedance
based on the cross section. otherwise we would need different trace widths
for every trace segment and we would need real-time 3D simulationd during
PCB layout design.
Exploring discontinuities on a real PCB (not on a test coupon) is is another
story. I was asking about the measurements for the test coupons (maybe I
forgot to mention). Normally (our) boards have hundreds of controlled
impedance interconnects, those at the first place should be correct based on
the cross section and test coupons. The rest is design practices, to make
shure we dont deviate too much with discontinuitise. Of course its probably
nice to characterise a full board, but in short development cycles, it
wouldn't work very well. but i dont know, maybe it would...
"Howard Johnson had an excellent video "
- if anyone knows where to find it, i would appreciate...
Jeff Loyer wrote:
"The TDR will report the same characteristic impedance of your trace
regardless of risetime"
- which impedance? the impedance at 1 GHz? or at 10 GHz? or at xxx GHz?
The characteristic impedance of a PCB trace depends on the frequency, since
Er and the loss tangent are frequency dependent, and there is skin effect
and others... so Z0(1GHz) is not equal to Z0(xxxGHz). So if a signal (lets
simplify it) is at xxx GHz, then its terminations should be best matched at
xxx GHz, and not at yyyGHz, so the board impedance should be correct at xxx
GHz, and not at yyyGHz.
Rob Sleigh wrote:
"Yes, it's a very common practice to characterize a PDB with a TDR whose
rise time is similar to the signal's rise time. It's up to the designer to
decide, but usually pick a faster rise time than the system rise time to
provide yourself with some margin."
-most of the PCB manufacturers we talked to, they never asked about
rise_time or frequency information of our signals, and when we tried to
provide these to them they said they have deleoped their super-duper test
setup which is based on tonns of measurements and it is accurate, and they
dont care about our signal's frequency or rise time, and we should just pay
and shut up... We tried In europe, north america and china. And the best
what they say is they compensate for frequencies up to 10GHz, without
knowing anything about our signal's freq/Tr.
The last one said they can't or don't change rise times on their TDR...
Kihong (Joshua) Kim wrote:
"maximum frequency that may capture the bandwidth of imformation in digital
world."
- I was trying to estimate rise times and bandwidth. Especially at the
receiver. I can't explain why it would be better than at the transmitter if
they are both matched terminated to Z0, but I have a feeling like that...
Normally at the receiver we have slower rise times. For example for PCIe and
SATA, the signal looks sinusoid, not that rectangular as at the transmitter.
So at a pattern 1010101010 the frequency would be f=data_rate/2. For other
interfaces, like DDR2/3, we can get rise times from simulation. So, I would
provide these to the PCB manufacturer to calculate trace widths and verify
by TDR/test-coupon measurements.
regards,
Istvan Nagy
CCT, UK
----- Original Message -----
From: "Kihong Joshua Kim" <joshuakh@xxxxxxxxx>
To: "Nagy István" <buenos@xxxxxxxxxxx>
Cc: <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, April 07, 2009 4:51 PM
Subject: [SI-LIST] Re: TDR impedance measurement and rise time
> Nagy,
> Couple of TDR measurements experience for real boards with known trace
> models and physical data will give you good sense of what TDR means.
> However, if you do not have time to build sample boards nor have TDR
> equipment...here is my help.
>
> Risetime conversion to frequency needs to be dealt with in-depth
> understanding of the topic. The quick rule of thumb equation mentioned
> in one of threaded mails is the maximum frequency that may capture the
> bandwidth of imformation in digital world. This is weird part because one
> might has question on why I am talking about digital bandwith when others
> discuss about analog nature of signal (rise time). Some excercise to
> uderstand Fourier analysis would give you an idea about what it meant.
>
> Anyhow, to get out of math and get the real sense of TDR with variety of
> sample boards.
> I had developed couple of years ago a virtual TDR head (IBIS TDR
> model) working just fine in any IBIS simualtion tools and I found out the
> paper in the internet (wow!). You could try sample boards as long as you
> have real board file and connector models and etc....
>
> If you google key words for IBIS TDR or TDR IBIS, you will find it easily.
> But just in case I attached here...
>
> http://www.cadence.com/rl/Resources/conference_papers/stp_TDR_in_IBIS_Kim.pdf
>
> Regards,
>
> Kihong (Joshua) Kim
> http://www.linkedin.com/in/joshuakh
>
>
>
> On Tue, Apr 7, 2009 at 10:39 AM, Loyer, Jeff <jeff.loyer@xxxxxxxxx> wrote:
>
>> Concerning measuring Z0:
>> The TDR will report the same characteristic impedance of your trace
>> regardless of risetime, assuming your trace is long enough and there
>> aren't
>> significant variations in impedance along its length.
>>
>> Typically, we have very similar 6" coupons for all our controlled
>> impedances. The board manufacturer will typically measure them with an
>> HVM-compatible TDR, probably about 200 ps risetime. We verify the
>> impedances with our ~17ps TDR.
>>
>> For simulations, on the other hand, you'll probably want a risetime
>> faster
>> than the projected risetime of your device (I'd guess about 2x; I don't
>> remember seeing it quantified). I typically see folks just go with the
>> risetime of the equipment, ~17ps, and ensure simulation match those
>> measurements. They may be a little conservative, but probably less work
>> in
>> the long run than trying to exactly justify any particular risetime.
>>
>> The advantages/disadvantages I can think of off-hand for fast risetimes
>> are:
>> 1) fast R.T. = resolution of finer features (discontinuities).
>> Unfortunately, this can also erroneously lead you to believe you need to
>> fix things that are "invisible" at your risetime of interest. Filtering
>> to
>> your risetime of interest can help you decide whether a discontinuity is
>> significant or not.
>> 2) fast R.T. = smaller probing geometries. It doesn't make sense to try
>> to
>> maintain a 15 ps risetime through a launch structure with 30 mil vias
>> spaced
>> 100 mils apart (such as might be used for manufacturing testing). Living
>> with slower risetimes can allow you to adopt much more HVM-friendly
>> launch
>> structures, including pogo-pinned probe connections.
>> 3) fast R.T. = less ESD protection. It's very easy to damage a TDR head
>> from static discharge - HVM-compatible TDR machines with slower risetimes
>> have ESD protection.
>>
>> If the scope or post-processing software doesn't have the ability to slow
>> your risetimes, you can buy filters from Picosecond Pulse labs (buy a
>> filter
>> at 0.35/RT). They also sell hardware to put out very fast risetimes.
>>
>> Jeff Loyer
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> On Behalf Of Nagy István
>> Sent: Tuesday, April 07, 2009 4:59 AM
>> To: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] TDR impedance measurement and rise time
>>
>> hi
>> If we measure PCB test coupons with a TDR to determine characteristic
>> impedance, should we set the rise time to be the same as the signal's
>> rise
>> time? is it possible to set it at all?
>>
>> what i found on the internet, the TDR manufacturers try to make rise time
>> to be as low as possible, like 15ps..., and thats it.
>>
>> If the rise time is always 15ps, then i think it will always measure the
>> impedance on a very high frequency, 2/t_rise or something, so several
>> gigahertz. Usually on a board we have different signals, some are running
>> 100MHz analog, some other are 800MT/s digital, or 2.5Gb/s digital.
>> shouldn't we do different setups for these, to get impedances on the
>> signal's operating frequency?
>>
>> Someone from a Fab told me, that the "TDR is not frequency dependent".
>> so
>> they dont take the signal's frequency into account.
>>
>> what is the correct handling of signaling frequency for impedance
>> measurements, and simulations?
>>
>> regards,
>>
>> Istvan Nagy
>> CCT
>>
>>
>>
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