[SI-LIST] Re: Switching FET Slew Rate
- From: Joseph Aday <adayjoseph-lists@xxxxxxxxx>
- To: npatel@xxxxxxxxxx
- Date: Fri, 20 Jul 2007 15:55:41 -0700 (PDT)
Hi Nikhil,
I'm glad to hear that you've been successfull with that approach. I should
have been clearer that that was what I meant.. applying the resistance in
series with the gate of the FET. I guess it is the charging up of the
gate-source capacitance that results in the voltage threshold of the FET being
crossed for turn-on.. and the additional resistance reduces the current flow,
thereby making it take longer to charge up and longer to switch (correct me if
I don't properly understand this?)
As for the thermal issue, I guess that would be because the FET remains in
the linear region longer before it goes into saturation? This is a really good
point.. thank you.
Thanks so much!!!
Joseph Aday
npatel@xxxxxxxxxx wrote:
In the past to reduce EMI out of SMPS I have added resistance to the
gate of the FET and had very good luck with it. However this causes
thermal issues. Check FET specs for thermal compliance.
Nikhil
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Joseph Aday
Sent: Friday, July 20, 2007 3:30 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Switching FET Slew Rate
Hi All,
I am curious to see if anyone has an opinion on the best way to slow
down the slew rate of a FET in a switching power supply.
One way is to add a series termination resistor at the final output,
but this would change the DC power level since it affects the DC drive
stength.
A second way is to add some source resistance to the FET. This seems
to be effective.
I'd love to hear others' opinions / experiences, if any? This is
intended to be an open question, not necessarily specific to any design.
Thank you,
Joseph Aday
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