[SI-LIST] Re: Switch Mode DC-DC Buck Regulator Efficiency

Avtaar,

Checkout one of Linear technology's datasheet on any number of their
sync buck controllers. They generally provide the formulas for
calculating the resistive and switching losses in the FETs

Mike


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Avtaar Singh
Sent: Monday, May 18, 2009 11:24 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Switch Mode DC-DC Buck Regulator Efficiency

Gurus:
I am trying to create a MOSFET loss spreadsheet for a Switch Mode DC-DC
buck
regulator. I had a few questions:

1) Should the conduction loss for the top and bottom MOSFET be thus:

   PC = D (IO2 x RDSON-HI x 1.3) (High-Side) PC = (1 - D) x (IO2 x
RDSON-LOx 1.3) (Low-Side)

or thus:

   PC = D2 (IO2 x RDSON-HI x 1.3) (High-Side) PC = (1 - D)2 x (IO2 x R
DSON-LO x 1.3) (Low-Side)

I am having a confusion that the 2nd set of formulae might be correct,
because the RMS current through the top MOSFET is DIO, and that through
the
bottom MOSFET is (1-D)IO

2) Is the gate charging loss generally very low in comparison to the
switching loss and conduction loss for the bottom MOSFET? Will the gate
charging loss not be considerable if the QG of the MOSFET is very very
high?


Regards,
Avtaar


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