[SI-LIST] Re: Slew Rate Calculation

Yes, a capacitor of 5pf with a diff termination of 100 ohms works fine.
As in my case (discrete implementation), I guess I can't do away with
the diff termination as compared to DIMMs which already provide them.

Regards,
Arjun Bingipur

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Cortex.Chen@xxxxxxxxxxxx
Sent: Thursday, November 30, 2006 2:35 PM
To: Bingipur, Arjun
Cc: bennyzhi@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Slew Rate Calculation

Could you try to replace tweaking resistor to capacitor?

Regards,

Cortex

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
=3D
On Behalf Of Bingipur, Arjun
Sent: Thursday, November 30, 2006 4:35 PM
To: si-list@xxxxxxxxxxxxx
Cc: bennyzhi@xxxxxxxxx
Subject: [SI-LIST] Re: Slew Rate Calculation


Sorry, a typo. It is DDR2.

Micron recommends a differential termination in the range of 100-120
ohms between the clock pairs, which will yield a high slew rate.
Probably because of the small load. But, my optimal slew rate is
achieved by tweaking the termination to around 33-35 ohms in the
simulation. Does this in any way influence the performance?

Regards,
Arjun Bingipur

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Benny Yan
Sent: Monday, November 27, 2006 8:30 AM
To: Bingipur, Arjun
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Slew Rate Calculation

Should it be DDR2?
It seems that the loading is too small, have you checked the model you
used?
like package,
C_comp...

On 11/25/06, Bingipur, Arjun <arjun.bingipur@xxxxxxxxxx> wrote:
>
>
> Hi,
>
> I'm doing a static timing analysis for determining the slew rate for
the
> differential clock signals of a DDR. When I do a slew rate derating
> calculation on the eye diagram, I end up with values of around 6V/ns
and
> I 'm unable to consider this value to compare with the address/command
> derating values to arrive at the correct setup and hold time values in
> the data sheet.
>
> The topology is such that a controller is driving a single DDR with a
> differential termination of 120 ohm connected close to the receiver
IC.
> Am I missing something here?
>
> Regards,
> Arjun Bingipur
>
>
>
>
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