[SI-LIST] Re: Slew Rate Calculation

I can think of a few:

Unmatched termination -> SI issues
Stronger load -> lower voltage swing
More current -> higher power dissipation
More current -> more power supply noise
Faster slew rate -> more radiation
Faster slew rate -> more crosstalk

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065
tom@xxxxxxxxxxxxx=20
www.teraspeed.com=20

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On
Behalf Of Bingipur, Arjun
Sent: Thursday, November 30, 2006 12:35 AM
To: si-list@xxxxxxxxxxxxx
Cc: bennyzhi@xxxxxxxxx
Subject: [SI-LIST] Re: Slew Rate Calculation



Sorry, a typo. It is DDR2.

Micron recommends a differential termination in the range of 100-120 =
ohms
between the clock pairs, which will yield a high slew rate. Probably =
because
of the small load. But, my optimal slew rate is achieved by tweaking the
termination to around 33-35 ohms in the simulation. Does this in any way
influence the performance?

Regards,
Arjun Bingipur

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Benny Yan
Sent: Monday, November 27, 2006 8:30 AM
To: Bingipur, Arjun
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Slew Rate Calculation

Should it be DDR2?
It seems that the loading is too small, have you checked the model you =
used?
like package, C_comp...

On 11/25/06, Bingipur, Arjun <arjun.bingipur@xxxxxxxxxx> wrote:
>
>
> Hi,
>
> I'm doing a static timing analysis for determining the slew rate for
the
> differential clock signals of a DDR. When I do a slew rate derating=20
> calculation on the eye diagram, I end up with values of around 6V/ns
and
> I 'm unable to consider this value to compare with the address/command =

> derating values to arrive at the correct setup and hold time values in =

> the data sheet.
>
> The topology is such that a controller is driving a single DDR with a=20
> differential termination of 120 ohm connected close to the receiver
IC.
> Am I missing something here?
>
> Regards,
> Arjun Bingipur
>
>
>
>
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