[SI-LIST] Re: Skin effect resistance in package pins for IR drop calculations

Mohan, there is not much point evaluating interconnect losses substantially 
above the cut-off between the die and the package.  Dally and Poulton does 
a decent treatment on this.

Steve.
At 04:52 AM 8/25/2005 +0100, Mohan R wrote:
>Steve,
>
>Currently we do not model the inductance for IR drop
>calculations.
>
>The core operating frequency is around 300Mhz and the
>rise/fall times would be  of the order of 100ps. But
>since this is core digital logic which
>charges/discharges the capacitance on the silicon die
>only,i thought that the current would be supplied by
>the decoupling capacitors on the die itself.
>
>In general,i am trying to understand the role of
>decoupling capacitors on silicon die and the current
>flow paths because of this decoupling capacitor
>addition.
>
>Regards,
>Mohan R
>
>--- steve weir <weirsi@xxxxxxxxxx> wrote:
>
> > Mohan, if you are not planning to model skin
> > resistance, does that mean
> > that you also do not plan to model loop inductance?
> > How slow is your circuit?
> >
> > Steve.
> > At 03:45 PM 8/24/2005 +0100, Mohan R wrote:
> > >Dear Experts,
> > >
> > >I had a question on the the pin(bondwire+leadframe)
> > >resistance to used for IR drop calculations for the
> > >digital core logic. Do i need to consider the
> > >resistance at DC or do i need to consider the
> > >resistance with skin effect included ?
> > >
> > >I was guessing that the high frequency current for
> > >digital core CMOS transistors  will be supplied by
> > >decoupling capacitors on the chip. Hence only the
> > DC
> > >current for charging the decoupling capacitors
> > would
> > >be provided by the package pins.
> > >
> > >Please comment.
> > >
> > >Thank you,
> > >Mohan R
> > >
> > >
> > >
> > >
> > >
> > >
> >
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