[SI-LIST] Re: Single crystal driving two different inputs of a chip

Should not be a problem.  In my previous board design, we connect four
clock inputs together to a signal oscillator, running 33MHz.

Well, you have to know what you are doing.  In rare case, the oscillator
has very weaker drive strength.  The clock inputs pins on the chip
should be close enough, not to rise up SI issue, etc.

Anyway, the concern about the jitter is too pessimistic to me.  Any
reason why and failing case?

Regards,
Joseph Wang


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Rohan Hubli
Sent: Tuesday, June 28, 2005 2:46 PM
To: ray.anderson@xxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Single crystal driving two different inputs of a
chip=20

I am talking about onnecting a single quartz
oscillator to two clock inputs

-----Original Message-----
From: Ray Anderson [mailto:ray.anderson@xxxxxxxxxx]
Sent: Tuesday, June 28, 2005 2:42 PM
To: si-list@xxxxxxxxxxxxx
Cc: Ray Anderson
Subject: [SI-LIST] Re: Single crystal driving two different inputs of a
chip=3D20


Are you asking about connecting a single crystal resonator to two
oscillators within a chip (I hope not...) or connecting a single quartz
oscillator to two clock inputs?

-Ray


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Rohan Hubli
Sent: Tuesday, June 28, 2005 2:38 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Single crystal driving two different inputs of a chip


Folks,=3D3D3D20

Can a single crystal be driving two different inputs of a chip that feed
=3D3D3D
into=3D3D3D20
two sensitive analog blocks within a chip. Has anyone had any experience
=3D3D3D

doing this kind of a thing on the board ?=3D3D3D20

We are facing an issue where a 27Mhz crystal clock needs to be hooked up
=3D3D3D
to drive=3D3D3D20
two sensitive analog cores.=3D3D3D20

If we make the connection internal to the chip then the jitter due to =
=3D
=3D3D
=3D3D3D
(trace delay + buffer delay + process variations)=3D3D3D20
has significant impact on the audio quality.

Not to mention the fact that any issues that surface and subsequent =3D
=3D3D3D
fixes with this approach will have significant=3D3D3D20
respin costs for the chip.=3D3D3D20

Your inputs would be greatly appreciated.=3D3D3D20

Thanks
Rohan=3D3D3D20
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