[SI-LIST] Re: Simulation Problem

manish bhakuni wrote:

>  
>Dear Sir/Mam
>       How do i tackle problems of "negative mos conductance" and "internal 
> time step too small for transient analysis" while simulating prelayout and 
> post layout modules of my Multiplier.
>       Plz also help me in Radix-16 Booth Encoding for my multiplier
>Manish Bhakuni
>  
>

For your first problem see the si-list FAQ at the following URL:

http://si-list.org/wiki/wiki.pl?Hspice_DC_And_Transient_Convergence_Problems


Your second question is somewhat outside the scope of this group.

-Ray Anderson

 
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