[SI-LIST] Re: Signal crossing Split plane
- From: Charles Harrington <ch_harrington@xxxxxxxxx>
- To: Scott McMorrow <scott@xxxxxxxxxxxxx>
- Date: Thu, 6 Dec 2007 13:14:11 -0800 (PST)
Scott,
I need no credibility from your eyes, because you've got none on mine.
You believe in friendship, biographies, self-praise, credentials, experience
etc.
I don't need to prove to you that I have any experience and I'm hiding from
no one. If you wish, go ahead and consder that I have no experience. I'm fine
with that.
You always take sides unnecessarily in this list, especially when the posting
comes from your friend or some one you know his biography. That's wrong.
I believe in nothing but the facts. Go ahead and disprove the facts, if you
can, and forget about my biography.
Why didn't you name the tool, if you know any? You can't believe me because
you don't know my biography. Why didn't you propose the methodology Chris
needed?
Well, I hope Chris is satisfied with your answer. To me you wrote much and
said nothing, because you are blind with other matters that have nothing to do
with the facts.
I have accussed no one. I'm throwing darts at no one and will never do that.
Scott McMorrow <scott@xxxxxxxxxxxxx> wrote:
Charles,
You said: "I disagree with Yuriy that a tool can define the boundaries
of discontinuties and decompose the channel. If he still believe this is
true, then he should name the tool."
IMO, there is no reason why a PCB SI tool cannot do exactly what Yuriy
says. That one does not now, does not preclude the possibility. Since
a tool based on a physical layout, netlist, and driver locations has
knowledge of all signal paths, and direction of signal travel, it would
be possible to automate the process of defining appropriate TEM and
Quasi-TEM boundaries, placing ports, performing full-wave extractions,
caching the results for other identical structures, and then integrating
the sub-circuits into a complete end-to-end model. I also do not see a
reason why it would not be possible to identify "problematic" structures
where well-defined return paths do not exist over the bandwidth of
interest, warn the user of the inherent errors in modeling, and possibly
even suggest alternatives to modify the structure. (Do not pick nits
with me over the details, or assume that because I have not included
every detail that I am somehow unaware of them. You would be wrong.)
The problem is in the size of "real" problems. You can argue all day
about higher order modes, and appropriate boundary definitions. These
have little relevance for a designer like Chris Cheng who is trying to
implement real system boards that have hundreds of 3, 6, 10 Gbps links,
and the necessary thousands of single-ended DDR-XYZ memory signals to
support those aggregated data rates, running at 533, 666, 1066, 1333,
and 1666 Mbps in his future systems. Although Chris is quite capable
of defining structures to model and simulate, and quite capable of
performing the modeling himself, his problem is one of sheer time,
volume and space.
Chris' problem boils down to two very basic questions:
1) Is there a tool and methodology that can help to engineer a reliable
system, free of SI, PI and EMI problems, within his product engineering
time window?
2) If not, when do I know, how do I know, that I must spend the time to
run full-wave tools to characterize and define the localized boundary
regions of the design?
Charles, you have been sitting in the background, hiding in anonymity,
throwing darts at Yuriy, when IMO they are unjustified. You would be
well advised to be a professional, ask questions and clarifications,
rather than make accusations. Please feel free to provide us with your
experience and credentials, rather than questioning Yuriy's. It would
help your credibility in my eyes.
regards,
Scott
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
Charles Harrington wrote:
> Chris,
>
> I completely agree with you. We need methods rather than just validated tools.
>
> I disagree with Yuriy that a tool can define the boundaries of discontinuties
> and decompose the channel. If he still believe this is true, then he should
> name the tool.
>
> Channel decomposition is a very old and simple procedure to impement. This I
> agree with Yuriy. But what Yuriy does not understand is that you can do
> decomposition only when you have one dominant wave mode at points or
> interfaces along the channel where you wish to do the decomposition. Let me
> explain what I mean. If you have a stripline, competely surrounded by a
> homogeous dielectric and losses can be neglected, then the TEM approximation
> can be used. Even if this stripline is as long as 1 km, you can decompose it
> and use quasi-static or even static approximations to analyse the different
> segments. These segments can later be integrated together. But when ever you
> have higher order modes, then straight-forward decomposition, which is
> implemented in most tools, fails. As Prof. R. Collins (field theory of guided
> waves) explains, once there are discontinuities, then the waves at the output
> of the segment containing the discontinuity will have a combination of the
> dominant
> modes (which you can competely characterize) and higher order modes (which
> you may not even know). These waves will then serve as incident waves to the
> second segment and so on. That's why in most tools, it is recommended to do
> decomposition only at points where the higher order modes have decayed. The
> user must define interfaces or points along the channel where the higher
> order modes have decayed and only the main mode (which propagates power) is
> present. This is one of the motivations why boundaries of discontinuties are
> defined. So, don't rely on tools to do channel decomposition whenever you
> have discontinuties at higher frequencies. Remember, at lower frequencies
> most of the effects of the highe order modes can be neglected.
> I am sure no body in this list (including myself) will be able to propose you
> a solution much better than the one you proposed yourself in your previous
> mail. Below, I will try to outline your methodology. Please correct me, if I
> don't understand something.
>
> 1. Characterise the 3D geometies for your PCB technology considering the
> return paths, plane stitches etc. at your frequencies of intertest. You may
> consider the highest frequency. Whenever discontinuties are placed too close
> to each other, then you consider them as one discontinutity and use a 3D
> field solver to compute the fied solution.
> 2. Use a statistical method to make sure you cover possible dimensions of the
> 3D geometries (such as via pads, via holes, stitcing vias and so on) and
> what-if scenarios.
> 3. Place your design rules in a data base for your post route verification
> analysis.
>
> I think if you proceed as you proposed yourself, then you will not encounter
> any uncalculated discontinuity, because you define your layout yourself. You
> can always localize any discontinuity you encounter. You just have to make
> sure that the return current is kept close to signal current. There is
> nothing new or difficult in this. Dr. Howard Johnson in his book on advanced
> black magic explains this very well.
>
> I hope it helps. If not, I'm sorry, I can not help you further.
>
> Best regards
> Charles
>
>
>
>
>
>
> Chris Cheng wrote:
> JP,
> I have no beef in who has a better 3D algorithm. My question is specifically
> on methodology to both Charles and Yuriy in integrating 3D models in a system
> environment and I didn't find Yuriy pimping his own tool in his response to
> me. In fact I think his description is somewhat closer to what Charles has
> been saying, there are non-localize models one has to take into consideration.
> I am just looking out from my short bus asking all the experts you mention to
> chime in. Namely, what is the correct methodology to integrate 3D models in a
> complete system interconnect simulation environment.
> As far as I know there are not that many brave souls that model the entire
> system interconnect in one big giant 3D full wave model from end to end. That
> means at certain point of time the model is partitioned, most likely between
> pure interconnect (lossy line) and discontinuity (3D models).
> I think Yuriy correctly point out some of the cases are not localizable and
> in those cases, what are you going to do ? What tool can tell me I can safely
> break my trace read from the PC CAD database at what distance before I have
> to extract my 3D model (as in case a) on my original question)? What tool can
> precompute the discontinuity in 3D and then calibrate out the ideal
> interconnect part out of the extended port (probably by some kind of pseudo
> TRL algorithm) so that a user can simply extract the trace length information
> from the PC CAD database and then just reuse the pre-compute 3D models
> everytime he encounter the discontinuity ?
> To me, the second option is very attractive because it gives the dumb user
> like me a very straight forward modeling methodology. All those via drills
> and return models, plane switches can be pre-compute and constrain in PCB
> design rules and the post route verification will be a snap by simply reading
> out the trace length and location of the discontinuity and substituting the
> pre-compute model.
> On the other hand, what if we hit one of those giant non-localize
> discontinuity ? What tool can fall back and extract the necessary area and
> model ?
> I am not an academic, I ship products. With that in mind, I need a
> methodology and not just a tool that can be validated to a terahertz.
> ________________________________
>
> From: Jean-Pierre Maurice [mailto:mauricejeanpierre@xxxxxxxxxxxxxx]
> Sent: Sat 12/1/2007 4:28 PM
> To: shlepnev@xxxxxxxxxxxxx; Chris Cheng; ch_harrington@xxxxxxxxx
> Cc: si-list@xxxxxxxxxxxxx
> Subject: RE: [SI-LIST] Re: Signal crossing Split plane
>
>
>
> Yuriy,
>
> stop confusing yourself and others with lengthy emails and explanations that
> have no proof.
>
> Which of the references you quote in the 40s or any other EM principle
> warrants you to model discontinuities the way you do in your application
> notes? I went through all the examples in your website using the link you
> provided ( http://www.simberian.com/AppNotes.php) and realized that you don't
> have even one example where you correlated your simulations with
> measurements. Why? Are you hiding something?
>
> At the beginning, Lee advised you to do some measurements. Charles also said
> the very thing, but in a rather harder way.
>
> I may disagree with the way Charles pointed this out to you, but there is a
> lot of truth in everything he said, especially regarding your models. Indeed,
> the models in your application notes are not correct and also misleading, I
> would say. You make terrible claims about your solver's ability to compute
> complex multilayer geometries and yet provide no example to make your case
> solid.
>
> In the case of via-hole modeling; If you have now learned and agree that
> via-holes are not just barrels and pads as you represent them in your notes,
> and if you now also agree that you need to be far away with your ports, then
> why do you still have these unrealistic models in your application notes? You
> even go as far as posting them in this list. By doing so, you mislead the
> young and unexperienced. You even mislead the users of your solver. If you
> claim that any of the models (multilayer geometries, slots, via, planes,
> transmission lines, etc) in your application notes is correct, then show us
> how they match with measurement results.
>
> There are also a lot of weakness in the way you explain some fundamental
> issues which do not reflect the 25 years of experience you claim to have.
> Unlike Charles, I will not talk about that openly in this forum. May be
> privately, if you permit me. You even forge explanations to justify your
> solver and models. This is inappropriate.
>
> I am now on holidays. When I get back to work, I would like to evaluate your
> solver using some of our multilayer geometries (if you provide me the 3 day
> evaluation license you promise on your website). As long as I don't see any
> good correlation with measurements and your simulation models are also weak,
> then there is no way I can believe you.
>
> Chris: I don't think Yuriy is the person to ask questions concerning real PCB
> designs when he can not provide realistic examples in the application notes
> of his own solver. If you don't believe me, use the link given above. Charles
> too is a bit impolite, I would say. There are a lot of other well respected
> experts in this forum (Steve, Istvan, Lee, Eric Bogatin etc) from whom I
> learn a lot. I think they will give you real answers, not some theory that
> does not help.
>
> Best regards
> Jean Pierre
>
>
>
>
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