[SI-LIST] Re: Signal crossing Split plane

Dear Folks,

You may be interested in reading the book "Power Integrity Modeling and
Design for Semiconductors and Systems"
www.prenhallprofessional.com/title/0136152066

There is material on signal line referencing which includes model to
hardware correlation for split planes. In addition you can download the
software from www.powerintegrity.net to reproduce some of the examples in
the book.

Best Regards,
Madhavan
> Charles,
>
> You said:  "I disagree with Yuriy that a tool can define the boundaries=20
> of discontinuties and decompose the channel. If he still believe this is =
>
> true, then he should name the tool."
>
> IMO, there is no reason why a PCB SI tool cannot do exactly what Yuriy=20
> says.  That one does not now, does not preclude the possibility.   Since =
>
> a tool based on a physical layout, netlist, and driver locations has=20
> knowledge of all signal paths, and direction of signal travel, it would=20
> be possible to automate the process of defining appropriate TEM and=20
> Quasi-TEM boundaries, placing ports, performing full-wave extractions,=20
> caching the results for other identical structures, and then integrating =
>
> the sub-circuits into a complete end-to-end model.  I also do not see a=20
> reason why it would not be possible to identify "problematic" structures =
>
> where well-defined return paths do not exist over the bandwidth of=20
> interest, warn the user of the inherent errors in modeling, and possibly =
>
> even suggest alternatives to modify the structure.   (Do not pick nits=20
> with me over the details, or assume that because I have not included=20
> every detail that I am somehow unaware of them.  You would be wrong.)
>
> The problem is in the size of "real" problems.  You can argue all day=20
> about higher order modes, and appropriate boundary definitions.  These=20
> have little relevance for a designer like Chris Cheng who is trying to=20
> implement real system boards that have hundreds of 3, 6, 10 Gbps links,=20
> and the necessary thousands of single-ended DDR-XYZ memory signals to=20
> support those aggregated data rates, running at 533, 666, 1066, 1333,=20
> and 1666 Mbps in his future systems.   Although Chris is quite capable=20
> of defining structures to model and simulate, and quite capable of=20
> performing the modeling himself, his problem is one of sheer time,=20
> volume and space.
>
> Chris' problem boils down to two very basic questions:
>
> 1) Is there a tool and methodology that can help to engineer a reliable=20
> system, free of SI, PI and EMI problems, within his product engineering=20
> time window?
>
> 2) If not, when do I know, how do I know, that I must spend the time to=20
> run full-wave tools to characterize and define the localized boundary=20
> regions of the design?
>
>
> Charles, you have been sitting in the background, hiding in anonymity,=20
> throwing darts at Yuriy, when IMO they are unjustified.    You would be=20
> well advised to be a professional, ask questions and clarifications,=20
> rather than make accusations.  Please feel free to provide us with your=20
> experience and credentials, rather than questioning Yuriy's.  It would=20
> help your credibility in my eyes.
>
>
> regards,
>
> Scott
>
>
>
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
> (401) 284-1827 Business
> (401) 284-1840 Fax
>
> http://www.teraspeed.com
>
> Teraspeed=AE is the registered service mark of
> Teraspeed Consulting Group LLC
>
>
>
> Charles Harrington wrote:
>> Chris,
>>   =20
>>   I completely agree with you. We need methods rather than just validat=
> ed tools.
>>   =20
>>   I disagree with Yuriy that a tool can define the boundaries of discon=
> tinuties and decompose the channel. If he still believe this is true, the=
> n he should name the tool.
>>   =20
>>   Channel decomposition is a very old and simple procedure to impement.=
>  This I agree with Yuriy. But what Yuriy does not understand is that you =
> can do decomposition only when you have one dominant wave mode at points =
> or interfaces along the channel where you wish to do the decomposition. L=
> et me explain what I mean. If you have a stripline, competely surrounded =
> by a homogeous dielectric and losses can be neglected, then the TEM appro=
> ximation can be used. Even if this stripline is as long as 1 km, you can =
> decompose it and use quasi-static or even static approximations to analys=
> e the different segments. These segments can later be integrated together=
> =2E But when ever you have higher order modes, then straight-forward deco=
> mposition, which is implemented in most tools, fails. As Prof. R. Collins=
>  (field theory of guided waves) explains, once there are discontinuities,=
>  then the waves at the output of the segment containing the discontinuity=
>  will have a combination of the dominant
>>  modes (which you can competely characterize) and higher order modes (w=
> hich you may not even know). These waves will then serve as incident wave=
> s to the second segment and so on. That's why in most tools, it is recomm=
> ended to do decomposition only at points where the higher order modes hav=
> e decayed. The user must define interfaces or points along the channel wh=
> ere the higher order modes have decayed and only the main mode (which pro=
> pagates power) is present. This is one of the motivations why boundaries =
> of discontinuties are defined. So, don't rely on tools to do channel deco=
> mposition whenever you have discontinuties at higher frequencies. Remembe=
> r, at lower frequencies most of the effects of the highe order modes can =
> be neglected.=20
>>   I am sure no body in this list (including myself) will be able to pro=
> pose you a solution much better than the one you proposed yourself in you=
> r previous mail. Below, I will try to outline your methodology. Please co=
> rrect me, if I don't understand something.
>>   =20
>>   1. Characterise the 3D geometies for your PCB technology considering =
> the return paths, plane stitches etc. at your frequencies of intertest. Y=
> ou may consider the highest frequency. Whenever discontinuties are placed=
>  too close to each other, then you consider them as one discontinutity an=
> d  use a 3D field solver to compute the fied solution.
>>   2. Use a statistical method to make sure you cover possible dimension=
> s of the 3D geometries (such as via pads, via holes, stitcing vias and so=
>  on) and what-if scenarios.
>>   3. Place your design rules in a data base for your post route verific=
> ation analysis.
>>   =20
>>   I think if you proceed as you proposed yourself, then you will not en=
> counter any uncalculated discontinuity, because you define your layout yo=
> urself. You can always localize any discontinuity you encounter. You just=
>  have to make sure that the return current is kept close to signal curren=
> t. There is nothing new or difficult in this. Dr. Howard Johnson in his b=
> ook on advanced black magic explains this very well.
>>   =20
>>   I hope it helps. If not, I'm sorry, I can not help you further.
>>   =20
>>   Best regards
>>   Charles
>>   =20
>>  =20
>> =20
>>   =20
>>   =20
>>  =20
>> Chris Cheng <Chris.Cheng@xxxxxxxx> wrote:
>>   JP,
>> I have no beef in who has a better 3D algorithm. My question is specifi=
> cally on methodology to both Charles and Yuriy in integrating 3D models i=
> n a system environment and I didn't find Yuriy pimping his own tool in hi=
> s response to me. In fact I think his description is somewhat closer to w=
> hat Charles has been saying, there are non-localize models one has to tak=
> e into consideration.
>> I am just looking out from my short bus asking all the experts you ment=
> ion to chime in. Namely, what is the correct methodology to integrate 3D =
> models in a complete system interconnect simulation environment.
>> As far as I know there are not that many brave souls that model the ent=
> ire system interconnect in one big giant 3D full wave model from end to e=
> nd. That means at certain point of time the model is partitioned, most li=
> kely between pure interconnect (lossy line) and discontinuity (3D models)=
> =2E=20
>> I think Yuriy correctly point out some of the cases are not localizable=
>  and in those cases, what are you going to do ? What tool can tell me I c=
> an safely break my trace read from the PC CAD database at what distance b=
> efore I have to extract my 3D model (as in case a) on my original questio=
> n)? What tool can precompute the discontinuity in 3D and then calibrate o=
> ut the ideal interconnect part out of the extended port (probably by some=
>  kind of pseudo TRL algorithm) so that a user can simply extract the trac=
> e length information from the PC CAD database and then just reuse the pre=
> -compute 3D models everytime he encounter the discontinuity ?
>> To me, the second option is very attractive because it gives the dumb u=
> ser like me a very straight forward modeling methodology. All those via d=
> rills and return models, plane switches can be pre-compute and constrain =
> in PCB design rules and the post route verification will be a snap by sim=
> ply reading out the trace length and location of the discontinuity and su=
> bstituting the pre-compute model.=20
>> On the other hand, what if we hit one of those giant non-localize disco=
> ntinuity ? What tool can fall back and extract the necessary area and mod=
> el ?
>> I am not an academic, I ship products. With that in mind, I need a meth=
> odology and not just a tool that can be validated to a terahertz.=20
>> ________________________________
>>
>> From: Jean-Pierre Maurice [mailto:mauricejeanpierre@xxxxxxxxxxxxxx]
>> Sent: Sat 12/1/2007 4:28 PM
>> To: shlepnev@xxxxxxxxxxxxx; Chris Cheng; ch_harrington@xxxxxxxxx
>> Cc: si-list@xxxxxxxxxxxxx
>> Subject: RE: [SI-LIST] Re: Signal crossing Split plane
>>
>>
>>
>> Yuriy,
>>
>> stop confusing yourself and others with lengthy emails and explanations=
>  that have no proof.
>>
>> Which of the references you quote in the 40s or any other EM principle =
> warrants you to model discontinuities the way you do in your application =
> notes? I went through all the examples in your website using the link you=
>  provided ( http://www.simberian.com/AppNotes.php) and realized that you =
> don't have even one example where you correlated your simulations with me=
> asurements. Why? Are you hiding something?=20
>>
>> At the beginning, Lee advised you to do some measurements. Charles also=
>  said the very thing, but in a rather harder way.
>>
>> I may disagree with the way Charles pointed this out to you, but there =
> is a lot of truth in everything he said, especially regarding your models=
> =2E Indeed, the models in your application notes are not correct and also=
>  misleading, I would say. You make terrible claims about your solver's ab=
> ility to compute complex multilayer geometries and yet provide no example=
>  to make your case solid.=20
>>
>> In the case of via-hole modeling; If you have now learned and agree tha=
> t via-holes are not just barrels and pads as you represent them in your n=
> otes, and if you now also agree that you need to be far away with your po=
> rts, then why do you still have these unrealistic models in your applicat=
> ion notes? You even go as far as posting them in this list. By doing so, =
> you mislead the young and unexperienced. You even mislead the users of yo=
> ur solver. If you claim that any of the models (multilayer geometries, sl=
> ots, via, planes, transmission lines, etc) in your application notes is c=
> orrect, then show us how they match with measurement results.=20
>>
>> There are also a lot of weakness in the way you explain some fundamenta=
> l issues which do not reflect the 25 years of experience you claim to hav=
> e. Unlike Charles, I will not talk about that openly in this forum. May b=
> e privately, if you permit me. You even forge explanations to justify you=
> r solver and models. This is inappropriate.=20
>>
>> I am now on holidays. When I get back to work, I would like to evaluate=
>  your solver using some of our multilayer geometries (if you provide me t=
> he 3 day evaluation license you promise on your website). As long as I do=
> n't see any good correlation with measurements and your simulation models=
>  are also weak, then there is no way I can believe you.=20
>>
>> Chris: I don't think Yuriy is the person to ask questions concerning re=
> al PCB designs when he can not provide realistic examples in the applicat=
> ion notes of his own solver. If you don't believe me, use the link given =
> above. Charles too is a bit impolite, I would say. There are a lot of oth=
> er well respected experts in this forum (Steve, Istvan, Lee, Eric Bogatin=
>  etc) from whom I learn a lot. I think they will give you real answers, n=
> ot some theory that does not help.=20
>>
>> Best regards
>> Jean Pierre
>>
>>
>>
>>
>> This email and any attachments thereto may contain private, confidentia=
> l, and privileged material for the sole use of the intended recipient. An=
> y review, copying, or distribution of this email (or any attachments) by =
> others is strictly prohibited. If you are not the intended recipient, ple=
> ase contact the sender immediately and permanently delete the original an=
> d any copies of this email and any attachments thereto.
>>
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-- 
Madhavan Swaminathan
Joseph M. Petit Professor in Electronics
Deputy Director, Microsystems Packaging Research Center
School of Electrical and Computer Engg.
777, Atlantic Drive
Georgia Institute of Technology
Atlanta, GA 30332-0250
Ph: (404) 894-3340

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