[SI-LIST] Re: Signal Integrity openings in Cisco, Shanghai, China
- From: Amit KUMAR STE <amit.kumar@xxxxxxxxxxxxxx>
- To: "Amit Agrawal (amiagra2)" <amiagra2@xxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 7 Oct 2011 06:58:11 +0200
Hello Amit ,
I am very keen for this job.
I have prior experience of SI/PI.
Kindly consider me for this job. I am attaching my resume with this mail.
Regards
Amit
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Amit Agrawal (amiagra2)
Sent: Thursday, October 06, 2011 7:01 AM
To: si-list@xxxxxxxxxxxxx
Cc: Amit Agrawal (amiagra2)
Subject: [SI-LIST] Signal Integrity openings in Cisco, Shanghai, China
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We have three full time Signal Integrity openings in Cisco, Shanghai,
China. The job description is given below. The req # are: R904300,
R904301, R904302. If you are interested you can apply directly and also
you can send me your resume.
Regards,
Amit Agrawal
Amit P Agrawal, Ph.D.
Senior Manager, Hardware Engineering
Ethernet Switching Technology Group
amiagra2@xxxxxxxxx <mailto:amiagra2@xxxxxxxxx>
Phone: 408 424 2732
Mobile: 408 666 8452
Fax: 408 853 2404
Job Description:
An experienced signal integrity engineer is being sought for design and
analysis of high speed interfaces and power distribution network. The
successful candidate will be part of signal integrity and Power
Integrity team and will participate in the definition of chip, package,
printed circuit board (PCB), and system interconnects. Within a
concurrent engineering environment, the individual will be part of a
larger team with system architects, logic designers, ASIC engineers, and
SI engineers in creation of next generation networking products.
This group works on present and next-generation cost-sensitive yet high
performance and high volume products.
Your responsibilities will include but not be limited to:
- Working experience in high speed serial I/O applications, PLLs,
transceiver/SERDES operations
- Definition of signaling and package technology for high performance
ASICs
- Simulating and/or analyzing and/or generating power delivery network
requirements
- Understanding signal integrity and timing in order to budget and
evaluate trade-offs between design parameters to determine a solution
space that is high volume manufacturable
- Generating the routing requirements and electrical margins for
specific interfaces and verifying their correctness
Typically requires MSEE/Ph.D combined with 2-7 years of related
experience, Proficiency with spice (or equivalent) circuit simulation,
field-solver and time/frequency domain analysis, familiarity with high
speed serdes design, PLL and LVDS, CML and other high-performance I/O
technologies, ASIC design experience with I/O selection and
simulation/validation, solid background on transmission line theory are
necessary. In depth understanding of electromagnetic is plus. Experience
with available CAD tools such as HSPICE, HFSS, FDTD tools, MoM tools,
Sigrity, PAKSI-E, Sentinel-PI, Siwave, Q3D, Agilent ADS, Cadence SI
tools or related tools is required. Experience correlating simulation
results with lab measurements using oscilloscopes, TDRs, VNAs, and
spectrum analyzers is a plus. Self motivation, teamwork and strong
communication skills are essential.
Education:
Typically requires MSEE/Ph.D combined with 2-7 years of related
experience
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