[SI-LIST] Signal Integrity Position

Intel's platform design group has an immediate opening of a contract
position in Santa Clara, CA for a senior signal integrity engineer in
the area of board level interconnection simulation. This person will be
part of a highly skilled validation platform design team performing
board level design and signal integrity analysis for high performance
Intel CPU and chipsets. 
 

Responsibilities: 

Deliverables: Signal integrity simulations and analysis of  multi-Gbit
serial bus interconnects to derive design solution space for board level
design and physical layout. He/she will also be responsible for
electrical model creation of interconnects and creation of SPICE
netlist for simulation. The engineer will work closely with silicon
design teams, board designers and fab house to optimize the system
design.  

 

Skills/Knowledge: 

 

Required: 

* MSEE/PhD or equivalent  
* At least 3 years experience in electronics packaging and interconnect 
* Good understanding of the materials, physics, and principles of
interconnection technologies such as equalization

* Experience performing multi-Gbit serial bus simulations, eye-diagram
analysis and deriving design rules for layout

* Experience with HSPICE

* Experience with RLCG parameter extraction tools, such as XFX
* Good teamwork and organization skills
* Strong verbal and written communication skills

 

Plus: 

* 5+ years Experience in package/board design or chip I/O design  

* Good knowledge of PCI-Express electricals
* Experience with board CAD tools, specially Cadence

* Experience with Ansoft Q3D or HFSS for connector and socket modeling

* Knowledge of microwave engineering

* Experience programming with Perl

 

Please send your resume to me: 
Subas Bastola

subas.bastola@xxxxxxxxx
Intel Corporation 

2200 Mission College Blvd
Santa Clara CA 95054

 


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